From: Stefan Roese Date: Wed, 30 Jan 2008 14:35:50 +0000 (+0100) Subject: ppc4xx: Fix GPIO configuration for pcs440ep X-Git-Tag: v1.3.2-rc1~7^2^2^2~3 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=e1d1429b49b0ee58c80f8c7b29c1ebaf8be7f5f1;p=u-boot ppc4xx: Fix GPIO configuration for pcs440ep The SRD0_PFC0 register was not configured correctly to enable the GPIO's 49-63 for GPIO. They have been configured as trace signals. This patch fixes this by clearing the corresponding bit. Signed-off-by: Stefan Roese --- diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index 90e99d3dca..96adbc915d 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -175,7 +175,7 @@ int board_early_init_f(void) *-------------------------------------------------------------------*/ mfsdr(sdr_pci0, reg); mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ - mtsdr(sdr_pfc0, 0x00000100); /* Pin function: enable GPIO49-63 */ + mtsdr(sdr_pfc0, 0x00000000); /* Pin function: enable GPIO49-63 */ mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins, select IRQ5 */ return 0;