From: Jaehoon Chung Date: Tue, 26 Jul 2016 10:03:49 +0000 (+0900) Subject: mmc: sdhci: revert "mmc: sdhci: Claer high speed if not supported" X-Git-Tag: v2016.09-rc2~98^2~6 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=e1ea7c44d67dde263c13e1aef300cab408236994;p=u-boot mmc: sdhci: revert "mmc: sdhci: Claer high speed if not supported" This "commit 429790026021d522d51617217d4b86218cca5750" is wrong. SDHCI_QUIRK_NO_HISPD_BIT is for skipping to set CTRL_HISPD bit. For example, Exynos didn't have CTRL_HISPD. But Highspeed mode is supported. (This quirks doesn't mean that driver didn't support the Highseepd mode.) Note: If driver didn't support the Highspeed Mode, use or add the other quirks. After applied this patch, all Exynos SoCs are just running with 25MHz. Signed-off-by: Jaehoon Chung --- diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 1d6d2fde0d..4112223f24 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -554,9 +554,6 @@ int sdhci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth, cfg->host_caps |= MMC_MODE_8BIT; } - if (quirks & SDHCI_QUIRK_NO_HISPD_BIT) - cfg->host_caps &= ~(MMC_MODE_HS | MMC_MODE_HS_52MHz); - if (host_caps) cfg->host_caps |= host_caps;