From: Peng Fan <Peng.Fan@freescale.com>
Date: Sun, 6 Sep 2015 09:15:47 +0000 (+0800)
Subject: imx: mx6: correct enable_fec_anatop_clock
X-Git-Tag: v2015.10-rc5~48^2~5
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=e2748b416798be31f035c8314787bf1867005b57;p=u-boot

imx: mx6: correct enable_fec_anatop_clock

We should follow 'read->set/clr bit->write' flow for enable_fec_anatop_clock,
otherwise we may overridden configuration before enable_fec_anatop_clock.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Cc: Fabio Estevam <fabio.estevam@freescale.com>
---

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index ba6cc75a7b..11efd12c9a 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -535,6 +535,8 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
 	if (freq < ENET_25MHZ || freq > ENET_125MHZ)
 		return -EINVAL;
 
+	reg = readl(&anatop->pll_enet);
+
 	if (fec_id == 0) {
 		reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
 		reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);