From: Stefan Roese <sr@denx.de>
Date: Tue, 8 Nov 2005 08:00:09 +0000 (+0100)
Subject: Updated PCI mapping for esd CPCI2DP board.
X-Git-Tag: LABEL_2006_03_12_0025~74
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=ea339205a94706d8b9170bbd89e8c1373df9a92f;p=u-boot

Updated PCI mapping for esd CPCI2DP board.
Add support for error LED.
Patch by Matthias Fuchs, 07 Nov 2005
---

diff --git a/CHANGELOG b/CHANGELOG
index 5c6d68fff0..5747cb4be5 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,10 @@
 Changes for U-Boot 1.1.4:
 ======================================================================
 
+* Updated PCI mapping for esd CPCI2DP board.
+  Add support for error LED.
+  Patch by Matthias Fuchs, 07 Nov 2005
+
 * Fix MPC85xx PCI support (pci_register_hose() before pci config access)
   Patch by Stefan Roese, 07 Nov 2005
 
diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c
index 727640e9b5..b463f0e389 100644
--- a/board/esd/cpci2dp/cpci2dp.c
+++ b/board/esd/cpci2dp/cpci2dp.c
@@ -31,14 +31,17 @@ int board_early_init_f (void)
 	unsigned long cntrl0Reg;
 
 	/*
-	 * Setup GPIO pins (CS4 as GPIO)
+	 * Setup GPIO pins (CS4+CS7 as GPIO)
 	 */
 	cntrl0Reg = mfdcr(cntrl0);
-	mtdcr(cntrl0, cntrl0Reg | 0x00800000);
-
-	out32(GPIO0_OR,  CFG_INTA_FAKE | CFG_EEPROM_WP); /* set output pins to high */
-	out32(GPIO0_ODR, CFG_INTA_FAKE);                 /* INTA# is open drain */
-	out32(GPIO0_TCR, CFG_INTA_FAKE | CFG_EEPROM_WP); /* setup for output        */
+	mtdcr(cntrl0, cntrl0Reg | 0x00900000);
+
+        /* set output pins to high */
+	out32(GPIO0_OR,  CFG_INTA_FAKE | CFG_EEPROM_WP | CFG_PB_LED);
+        /* INTA# is open drain */
+	out32(GPIO0_ODR, CFG_INTA_FAKE);
+        /* setup for output */
+	out32(GPIO0_TCR, CFG_INTA_FAKE | CFG_EEPROM_WP);
 
 	/*
 	 * IRQ 0-15  405GP internally generated; active high; level sensitive
diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h
index 4a6a3f8515..756bb8ceac 100644
--- a/include/configs/CPCI2DP.h
+++ b/include/configs/CPCI2DP.h
@@ -146,9 +146,9 @@
 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
 #define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA	0xef600000	/* point to internal regs + PB0/1 */
+#define CFG_PCI_PTM2LA	0xef000000	/* point to internal regs + PB0/1 */
 #define CFG_PCI_PTM2MS  0xff000001      /* 16MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
@@ -237,11 +237,11 @@
 
 /* Memory Bank 2 (PB0) initialization					*/
 #define CFG_EBC_PB2AP		0x03004580  /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CFG_EBC_PB2CR		0xEF018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 3 (PB1) initialization				*/
 #define CFG_EBC_PB3AP		0x03004580  /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
-#define CFG_EBC_PB3CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
+#define CFG_EBC_PB3CR		0xEF118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
@@ -258,6 +258,7 @@
  * GPIO definitions
  */
 #define CFG_EEPROM_WP		(0x80000000 >> 13)   /* GPIO13 */
+#define CFG_PB_LED		(0x80000000 >> 16)   /* GPIO16 */
 #define CFG_INTA_FAKE		(0x80000000 >> 23)   /* GPIO23 */
 
 /*