From: Troy Kisky <troy.kisky@boundarydevices.com>
Date: Thu, 19 Jul 2012 08:18:05 +0000 (+0000)
Subject: mxc_i2c: clear i2sr before waiting for bit
X-Git-Tag: v2012.10-rc1~415^2~30
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=ea572d853eb03c6ac2021c21aae60891b5f92655;p=u-boot

mxc_i2c: clear i2sr before waiting for bit

Let's clear the sr register before waiting for
bit to be set, instead of clearing it after
hardware sets it. No real operational difference here,
but allows combining of i2c_imx_trx_complete and
i2c_imx_bus_busy in later patches.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
---

diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index d147dd5f34..57027ad4db 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -200,10 +200,8 @@ int i2c_imx_trx_complete(void)
 	int timeout = I2C_MAX_TIMEOUT;
 
 	while (timeout--) {
-		if (readb(&i2c_regs->i2sr) & I2SR_IIF) {
-			writeb(0, &i2c_regs->i2sr);
+		if (readb(&i2c_regs->i2sr) & I2SR_IIF)
 			return 0;
-		}
 
 		udelay(1);
 	}
@@ -215,6 +213,7 @@ static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte)
 {
 	int ret;
 
+	writeb(0, &i2c_regs->i2sr);
 	writeb(byte, &i2c_regs->i2dr);
 	ret = i2c_imx_trx_complete();
 	if (ret < 0)
@@ -346,7 +345,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
 	if (len == 1)
 		temp |= I2CR_TX_NO_AK;
 	writeb(temp, &i2c_regs->i2cr);
-	readb(&i2c_regs->i2dr);
+	writeb(0, &i2c_regs->i2sr);
+	readb(&i2c_regs->i2dr);		/* dummy read to clear ICF */
 
 	/* read data */
 	for (i = 0; i < len; i++) {
@@ -369,6 +369,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
 			writeb(temp, &i2c_regs->i2cr);
 		}
 
+		writeb(0, &i2c_regs->i2sr);
 		buf[i] = readb(&i2c_regs->i2dr);
 	}