From: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Date: Sat, 3 May 2008 04:51:28 +0000 (+0900)
Subject: [MIPS] cpu/mips/cache.S: Add dcache_enable
X-Git-Tag: v1.3.3-rc3~1^2~5^2~1
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=ea638951acead7f1086c908c0b9f086beab82a22;p=u-boot

[MIPS] cpu/mips/cache.S: Add dcache_enable

Recent bootelf command fixes (017e9b7925f74878d0e9475388cca9bda5ef9482,
"allow ports to override bootelf behavior") requires ports to have this
function.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---

diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S
index f593968320..428d251bf1 100644
--- a/cpu/mips/cache.S
+++ b/cpu/mips/cache.S
@@ -285,6 +285,22 @@ LEAF(dcache_disable)
 	jr	ra
 	END(dcache_disable)
 
+/*******************************************************************************
+*
+* dcache_enable - enable cache
+*
+* RETURNS: N/A
+*
+*/
+LEAF(dcache_enable)
+	mfc0	t0, CP0_CONFIG
+	ori	t0, CONF_CM_CMASK
+	xori	t0, CONF_CM_CMASK
+	ori	t0, CONF_CM_CACHABLE_NONCOHERENT
+	mtc0	t0, CP0_CONFIG
+	jr	ra
+	END(dcache_enable)
+
 #ifdef CFG_INIT_RAM_LOCK_MIPS
 /*******************************************************************************
 *