From: ntfreak Date: Thu, 26 Jul 2007 12:28:22 +0000 (+0000) Subject: - corrected stm32x_handle_options_write_command, incorrect options printed X-Git-Tag: v0.1.0~1095 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=eba4e394d834c5088f95412a6d3bdba622a691fc;p=openocd - corrected stm32x_handle_options_write_command, incorrect options printed - added prepare_reset_halt handler for cortex_m3 git-svn-id: svn://svn.berlios.de/openocd/trunk@184 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- diff --git a/src/flash/stm32x.c b/src/flash/stm32x.c index bb41f732..a09fa40d 100644 --- a/src/flash/stm32x.c +++ b/src/flash/stm32x.c @@ -736,7 +736,7 @@ int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char if (argc < 4) { - command_print(cmd_ctx, "stm32x options_write "); + command_print(cmd_ctx, "stm32x options_write "); return ERROR_OK; } diff --git a/src/server/server.c b/src/server/server.c index 4c4fdecc..3ad6f377 100644 --- a/src/server/server.c +++ b/src/server/server.c @@ -386,7 +386,8 @@ int server_loop(command_context_t *command_context) MSG msg; while (PeekMessage(&msg,NULL,0,0,PM_REMOVE)) { - if (msg.message==WM_QUIT) shutdown_openocd = 1; + if (msg.message == WM_QUIT) + shutdown_openocd = 1; } #endif } @@ -422,10 +423,10 @@ int server_init() SetConsoleCtrlHandler( ControlHandler, TRUE ); - signal(SIGINT, sig_handler); - signal(SIGTERM, sig_handler); - signal(SIGBREAK, sig_handler); - signal(SIGABRT, sig_handler); + signal(SIGINT, sig_handler); + signal(SIGTERM, sig_handler); + signal(SIGBREAK, sig_handler); + signal(SIGABRT, sig_handler); #endif diff --git a/src/target/armv7m.c b/src/target/armv7m.c index 335d0acc..5ab9c104 100644 --- a/src/target/armv7m.c +++ b/src/target/armv7m.c @@ -57,22 +57,22 @@ char* armv7m_exception_strings[] = char* armv7m_core_reg_list[] = { -/* Registers accessed through core debug */ + /* Registers accessed through core debug */ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", "xPSR", "msp", "psp", -/* Registers accessed through MSR instructions */ + /* Registers accessed through MSR instructions */ // "apsr", "iapsr", "ipsr", "epsr", "primask", "basepri", "faultmask", "control" }; char* armv7m_core_dbgreg_list[] = { -/* Registers accessed through core debug */ + /* Registers accessed through core debug */ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", "xPSR", "msp", "psp", -/* Registers accessed through MSR instructions */ + /* Registers accessed through MSR instructions */ // "dbg_apsr", "iapsr", "ipsr", "epsr", "primask", "basepri", "faultmask", "dbg_control" }; @@ -122,7 +122,6 @@ armv7m_core_reg_t armv7m_core_reg_list_arch_info[] = int armv7m_core_reg_arch_type = -1; - /* Keep different contexts for the process being debugged and debug algorithms */ enum armv7m_runcontext armv7m_get_context(target_t *target) { @@ -238,8 +237,8 @@ int armv7m_read_core_reg(struct target_s *target, int num) armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info; retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, ®_value); buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value); - armv7m->core_cache->reg_list[num].valid=1; - armv7m->core_cache->reg_list[num].dirty=0; + armv7m->core_cache->reg_list[num].valid = 1; + armv7m->core_cache->reg_list[num].dirty = 0; return ERROR_OK; } @@ -248,7 +247,7 @@ int armv7m_write_core_reg(struct target_s *target, int num) { int retval; u32 reg_value; - armv7m_core_reg_t * armv7m_core_reg; + armv7m_core_reg_t *armv7m_core_reg; /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; @@ -262,12 +261,12 @@ int armv7m_write_core_reg(struct target_s *target, int num) if (retval != ERROR_OK) { ERROR("JTAG failure"); - armv7m->core_cache->reg_list[num].dirty=1; + armv7m->core_cache->reg_list[num].dirty = 1; return ERROR_JTAG_DEVICE_ERROR; } - DEBUG("write core reg %i value 0x%x",num ,reg_value); - armv7m->core_cache->reg_list[num].valid=1; - armv7m->core_cache->reg_list[num].dirty=0; + DEBUG("write core reg %i value 0x%x", num , reg_value); + armv7m->core_cache->reg_list[num].valid = 1; + armv7m->core_cache->reg_list[num].dirty = 0; return ERROR_OK; } @@ -549,7 +548,7 @@ reg_cache_t *armv7m_build_reg_cache(target_t *target) reg_list[i].arch_type = armv7m_core_reg_arch_type; reg_list[i].arch_info = &arch_info[i]; } - + return cache; } diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index b342fce2..852326a7 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -67,7 +67,8 @@ target_type_t cortexm3_target = .assert_reset = cortex_m3_assert_reset, .deassert_reset = cortex_m3_deassert_reset, .soft_reset_halt = cortex_m3_soft_reset_halt, - + .prepare_reset_halt = cortex_m3_prepare_reset_halt, + .get_gdb_reg_list = armv7m_get_gdb_reg_list, .read_memory = cortex_m3_read_memory, @@ -98,7 +99,7 @@ int cortex_m3_clear_halt(target_t *target) ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); /* Write Debug Fault Status Register to enable processing to resume ?? Try with and without this !! */ ahbap_write_system_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr); - DEBUG(" NVIC_DFSR 0x%x",cortex_m3->nvic_dfsr); + DEBUG(" NVIC_DFSR 0x%x", cortex_m3->nvic_dfsr); return ERROR_OK; } @@ -128,15 +129,13 @@ int cortex_m3_exec_opcode(target_t *target,u32 opcode, int len /* MODE, r0_inval swjdp_common_t *swjdp = &cortex_m3->swjdp_info; u32 savedram; int retvalue; - - { - ahbap_read_system_u32(swjdp, 0x20000000, &savedram); - ahbap_write_system_u32(swjdp, 0x20000000, opcode); - ahbap_write_coreregister_u32(swjdp, 0x20000000, 15); - cortex_m3_single_step_core(target); - armv7m->core_cache->reg_list[15].dirty = 1; - retvalue = ahbap_write_system_atomic_u32(swjdp, 0x20000000, savedram); - } + + ahbap_read_system_u32(swjdp, 0x20000000, &savedram); + ahbap_write_system_u32(swjdp, 0x20000000, opcode); + ahbap_write_coreregister_u32(swjdp, 0x20000000, 15); + cortex_m3_single_step_core(target); + armv7m->core_cache->reg_list[15].dirty = 1; + retvalue = ahbap_write_system_atomic_u32(swjdp, 0x20000000, savedram); return retvalue; } @@ -167,7 +166,7 @@ int cortex_m3_endreset_event(target_t *target) DEBUG(" "); /* Enable debug requests */ ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); - if (!(cortex_m3->dcb_dhcsr&C_DEBUGEN)) + if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN ); /* Enable trace and dwt */ ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET ); @@ -207,7 +206,7 @@ int cortex_m3_examine_debug_reason(target_t *target) cortex_m3_common_t *cortex_m3 = armv7m->arch_info; swjdp_common_t *swjdp = &cortex_m3->swjdp_info; -/* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */ + /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */ /* only check the debug reason if we don't know it already */ if ((target->debug_reason != DBG_REASON_DBGRQ) @@ -393,21 +392,21 @@ enum target_state cortex_m3_poll(target_t *target) return TARGET_UNKNOWN; } - if (cortex_m3->dcb_dhcsr&S_RESET_ST) + if (cortex_m3->dcb_dhcsr & S_RESET_ST) { target->state = TARGET_RESET; return target->state; } - else if (target->state==TARGET_RESET) + else if (target->state == TARGET_RESET) { /* Cannot switch context while running so endreset is called with target->state == TARGET_RESET */ - DEBUG("Exit from reset with dcb_dhcsr %x", cortex_m3->dcb_dhcsr); + DEBUG("Exit from reset with dcb_dhcsr 0x%x", cortex_m3->dcb_dhcsr); cortex_m3_endreset_event(target); target->state = TARGET_RUNNING; prev_target_state = TARGET_RUNNING; } - if (cortex_m3->dcb_dhcsr&S_HALT) + if (cortex_m3->dcb_dhcsr & S_HALT) { target->state = TARGET_HALTED; @@ -429,13 +428,13 @@ enum target_state cortex_m3_poll(target_t *target) } /* - if (cortex_m3->dcb_dhcsr&S_SLEEP) + if (cortex_m3->dcb_dhcsr & S_SLEEP) target->state = TARGET_SLEEP; */ /* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script */ ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); - DEBUG("dcb_dhcsr %x, nvic_dfsr %x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, target_state_strings[target->state]); + DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, target_state_strings[target->state]); return target->state; } @@ -482,13 +481,13 @@ int cortex_m3_soft_reset_halt(struct target_s *target) /* registers are now invalid */ armv7m_invalidate_core_regs(target); - while (timeout<100) + while (timeout < 100) { retval = ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr); if (retval == ERROR_OK) { ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); - if ((dcb_dhcsr&S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH)) + if ((dcb_dhcsr & S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH)) { DEBUG("system reset-halted, dcb_dhcsr 0x%x, nvic_dfsr 0x%x", dcb_dhcsr, cortex_m3->nvic_dfsr); cortex_m3_poll(target); @@ -504,6 +503,23 @@ int cortex_m3_soft_reset_halt(struct target_s *target) return ERROR_OK; } +int cortex_m3_prepare_reset_halt(struct target_s *target) +{ + armv7m_common_t *armv7m = target->arch_info; + cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + + /* Enable debug requests */ + ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) + ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN ); + + /* Enter debug state on reset, cf. end_reset_event() */ + ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET ); + + return ERROR_OK; +} + int cortex_m3_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution) { /* get pointers to arch-specific information */ @@ -584,6 +600,7 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand /* Set/Clear C_MASKINTS in a separate operation */ if ((cortex_m3->dcb_dhcsr & C_MASKINTS) != (dcb_dhcsr & C_MASKINTS)) ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, dcb_dhcsr | C_HALT ); + /* Restart core */ ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, dcb_dhcsr ); target->debug_reason = DBG_REASON_NOTHALTED; @@ -667,7 +684,7 @@ int cortex_m3_step(struct target_s *target, int current, u32 address, int handle int cortex_m3_assert_reset(target_t *target) { int retval; - + DEBUG("target->state: %s", target_state_strings[target->state]); if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN) @@ -730,7 +747,7 @@ int cortex_m3_assert_reset(target_t *target) } int cortex_m3_deassert_reset(target_t *target) -{ +{ DEBUG("target->state: %s", target_state_strings[target->state]); /* deassert reset lines */ @@ -1265,7 +1282,7 @@ int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *ta target_read_u32(target, CPUID, &cpuid); if (((cpuid >> 4) & 0xc3f) == 0xc23) DEBUG("CORTEX-M3 processor detected"); - DEBUG("cpuid %x", cpuid); + DEBUG("cpuid: 0x%8.8x", cpuid); target_read_u32(target, NVIC_ICTR, &ictr); cortex_m3->intlinesnum = (ictr & 0x1F) + 1; @@ -1273,7 +1290,7 @@ int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *ta for (i = 0; i < cortex_m3->intlinesnum; i++) { target_read_u32(target, NVIC_ISE0 + 4 * i, cortex_m3->intsetenable + i); - DEBUG("interrupt enable[%i] = 0x%x", i, cortex_m3->intsetenable[i]); + DEBUG("interrupt enable[%i] = 0x%8.8x", i, cortex_m3->intsetenable[i]); } /* Setup FPB */ @@ -1282,7 +1299,7 @@ int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *ta cortex_m3->fp_num_code = (fpcr >> 4) & 0xF; cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF; cortex_m3->fp_code_available = cortex_m3->fp_num_code; - cortex_m3->fp_comparator_list=calloc(cortex_m3->fp_num_code+cortex_m3->fp_num_lit, sizeof(cortex_m3_fp_comparator_t)); + cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(cortex_m3_fp_comparator_t)); for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) { cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL; diff --git a/src/target/cortex_m3.h b/src/target/cortex_m3.h index 7061d668..d51c4a49 100644 --- a/src/target/cortex_m3.h +++ b/src/target/cortex_m3.h @@ -197,6 +197,7 @@ int cortex_m3_step(struct target_s *target, int current, u32 address, int handle int cortex_m3_assert_reset(target_t *target); int cortex_m3_deassert_reset(target_t *target); int cortex_m3_soft_reset_halt(struct target_s *target); +int cortex_m3_prepare_reset_halt(struct target_s *target); int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); diff --git a/src/target/cortex_swjdp.c b/src/target/cortex_swjdp.c index 0815f6ed..2a2267ff 100644 --- a/src/target/cortex_swjdp.c +++ b/src/target/cortex_swjdp.c @@ -439,7 +439,7 @@ int ahbap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) } if (errorcount > 1) { - WARNING("Block read error address %x, count %x", address, count); + WARNING("Block read error address 0x%x, count 0x%x", address, count); return ERROR_JTAG_DEVICE_ERROR; } } @@ -531,7 +531,7 @@ int ahbap_read_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) } if (errorcount > 1) { - WARNING("Block read error address %x, count %x", address, count); + WARNING("Block read error address 0x%x, count 0x%x", address, count); return ERROR_JTAG_DEVICE_ERROR; } } @@ -600,7 +600,7 @@ int ahbap_block_read_u32(swjdp_common_t *swjdp, u32 *buffer, int count, u32 addr } if (errorcount > 1) { - WARNING("Block read error address %x, count %x", address, count); + WARNING("Block read error address 0x%x, count 0x%x", address, count); return ERROR_JTAG_DEVICE_ERROR; } }