From: Jagannadha Sutradharudu Teki Date: Fri, 20 Sep 2013 13:09:47 +0000 (+0530) Subject: fpga: zynqpl: Add dcache flush support X-Git-Tag: v2014.01-rc1~116^2~2 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=ec4b73f09c384007b274b38052149025e080b138;p=u-boot fpga: zynqpl: Add dcache flush support Buffers must be cache and dma aligned. Signed-off-by: Jagannadha Sutradharudu Teki Signed-off-by: Michal Simek --- diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 717c0394ca..f2f49b56a6 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -177,8 +177,8 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) return FPGA_FAIL; } - if ((u32)buf_start & 0x3) { - u32 *new_buf = (u32 *)((u32)buf & ~0x3); + if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) { + u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN); printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, (u32)buf_start, (u32)new_buf, swap); @@ -284,6 +284,10 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) debug("%s: Source = 0x%08X\n", __func__, (u32)buf); debug("%s: Size = %zu\n", __func__, bsize); + /* flush(clean & invalidate) d-cache range buf */ + flush_dcache_range((u32)buf, (u32)buf + + roundup(bsize, ARCH_DMA_MINALIGN)); + /* Set up the transfer */ writel((u32)buf | 1, &devcfg_base->dma_src_addr); writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr);