From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Wed, 23 Dec 2015 15:09:33 +0000 (+0530)
Subject: drivers: spi: ti_qspi: do not hard code chip select for memory map configuration
X-Git-Tag: v2016.03-rc1~357
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=ec712f490d9cd04257376d6cc6d52778b174c435;p=u-boot

drivers: spi: ti_qspi: do not hard code chip select for memory map configuration

To enable memory map in dra7xx, specific chip select must be
written to control module register. But this hard coded to chip
select 1, fixing it by writing the specific chip select value to
control module register.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
---

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 26616ebc7a..d5a06b8494 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -41,7 +41,7 @@
 #define QSPI_WC_BUSY                    (QSPI_WC | QSPI_BUSY)
 #define QSPI_XFER_DONE                  QSPI_WC
 #define MM_SWITCH                       0x01
-#define MEM_CS                          0x100
+#define MEM_CS(cs)                      ((cs + 1) << 8)
 #define MEM_CS_UNSELECT                 0xfffff0ff
 #define MMAP_START_ADDR_DRA		0x5c000000
 #define MMAP_START_ADDR_AM43x		0x30000000
@@ -267,7 +267,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 		writel(MM_SWITCH, &qslave->base->memswitch);
 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
 		val = readl(CORE_CTRL_IO);
-		val |= MEM_CS;
+		val |= MEM_CS(slave->cs);
 		writel(val, CORE_CTRL_IO);
 #endif
 		return 0;