From: Andre Przywara Date: Mon, 2 Jan 2017 11:48:43 +0000 (+0000) Subject: sunxi: H3/A64: fix non-ODT setting X-Git-Tag: v2017.03-rc1~164^2~2 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=ed25486215148cb0a8ed4459aa74d04bacbcd3c3;p=u-boot sunxi: H3/A64: fix non-ODT setting According to Jens disabling the on-die-termination should set bit 5, not bit 1 in the respective register. Fix this. Reported-by: Jens Kuske Signed-off-by: Andre Przywara Reviewed-by: Jagan Teki --- diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c b/arch/arm/mach-sunxi/dram_sun8i_h3.c index fe9cf9a181..1311edaf32 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_h3.c +++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c @@ -414,6 +414,11 @@ static void mctl_sys_init(uint16_t socid, struct dram_para *para) udelay(500); } +/* These are more guessed based on some Allwinner code. */ +#define DX_GCR_ODT_DYNAMIC (0x0 << 4) +#define DX_GCR_ODT_ALWAYS_ON (0x1 << 4) +#define DX_GCR_ODT_OFF (0x2 << 4) + static int mctl_channel_init(uint16_t socid, struct dram_para *para) { struct sunxi_mctl_com_reg * const mctl_com = @@ -443,7 +448,8 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para) clrsetbits_le32(&mctl_ctl->dx[i].gcr, (0x3 << 4) | (0x1 << 1) | (0x3 << 2) | (0x3 << 12) | (0x3 << 14), - IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x2); + IS_ENABLED(CONFIG_DRAM_ODT_EN) ? + DX_GCR_ODT_DYNAMIC : DX_GCR_ODT_OFF); /* AC PDR should always ON */ setbits_le32(&mctl_ctl->aciocr, 0x1 << 1);