From: mlu Date: Mon, 10 Sep 2007 17:43:08 +0000 (+0000) Subject: - Fixed display of sector sizes in flash.c X-Git-Tag: v0.1.0~1073 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=ed36a8d15dfd04e47d23d5f1e09078f105785fb1;p=openocd - Fixed display of sector sizes in flash.c - Clean up, remove unused variables and code in armv7, cortex_m3 and stellaris code - Move restore_context from cortex_m3 to armv7m - Updated halt handling for cortex_m3 git-svn-id: svn://svn.berlios.de/openocd/trunk@206 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- diff --git a/src/flash/flash.c b/src/flash/flash.c index 9ca5f157..83b6fc37 100644 --- a/src/flash/flash.c +++ b/src/flash/flash.c @@ -267,8 +267,8 @@ int handle_flash_info_command(struct command_context_s *cmd_ctx, char *cmd, char else protect_state = "protection state unknown"; - command_print(cmd_ctx, "\t#%i: 0x%8.8x (0x%xkB) %s, %s", - j, p->sectors[j].offset, p->sectors[j].size, + command_print(cmd_ctx, "\t#%i: 0x%8.8x (0x%x %ikB) %s, %s", + j, p->sectors[j].offset, p->sectors[j].size, p->sectors[j].size>>10, erase_state, protect_state); } diff --git a/src/flash/stellaris.c b/src/flash/stellaris.c index 490b02cc..970c1d69 100644 --- a/src/flash/stellaris.c +++ b/src/flash/stellaris.c @@ -43,6 +43,7 @@ #include #include +#define DID0_VER(did0) ((did0>>28)&0x07) int stellaris_register_commands(struct command_context_s *cmd_ctx); int stellaris_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank); int stellaris_erase(struct flash_bank_s *bank, int first, int last); @@ -53,6 +54,7 @@ int stellaris_erase_check(struct flash_bank_s *bank); int stellaris_protect_check(struct flash_bank_s *bank); int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size); +int stellaris_read_part_info(struct flash_bank_s *bank); u32 stellaris_get_flash_status(flash_bank_t *bank); void stellaris_set_flash_mode(flash_bank_t *bank,int mode); u32 stellaris_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout); @@ -128,6 +130,12 @@ struct { {0,"Unknown part"} }; +char * StellarisClassname[2] = +{ + "Sandstorm", + "Fury" +}; + /*************************************************************************** * openocd command interface * ***************************************************************************/ @@ -169,7 +177,7 @@ int stellaris_register_commands(struct command_context_s *cmd_ctx) int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size) { - int printed; + int printed, device_class; stellaris_flash_bank_t *stellaris_info = bank->driver_priv; stellaris_read_part_info(bank); @@ -182,8 +190,16 @@ int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size) return ERROR_FLASH_OPERATION_FAILED; } - printed = snprintf(buf, buf_size, "\nLMI Stellaris information: Chip is class %i %s v%c.%i\n", - (stellaris_info->did0>>16)&0xff, stellaris_info->target_name, + if (DID0_VER(stellaris_info->did0)>0) + { + device_class = (stellaris_info->did0>>16)&0xFF; + } + else + { + device_class = 0; + } + printed = snprintf(buf, buf_size, "\nLMI Stellaris information: Chip is class %i(%s) %s v%c.%i\n", + device_class, StellarisClassname[device_class], stellaris_info->target_name, 'A' + (stellaris_info->did0>>8)&0xFF, (stellaris_info->did0)&0xFF); buf += printed; buf_size -= printed; @@ -211,7 +227,6 @@ int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size) u32 stellaris_get_flash_status(flash_bank_t *bank) { - stellaris_flash_bank_t *stellaris_info = bank->driver_priv; target_t *target = bank->target; u32 fmc; @@ -227,7 +242,7 @@ void stellaris_read_clock_info(flash_bank_t *bank) stellaris_flash_bank_t *stellaris_info = bank->driver_priv; target_t *target = bank->target; u32 rcc, pllcfg, sysdiv, usesysdiv, bypass, oscsrc; - unsigned long tmp, mainfreq; + unsigned long mainfreq; target_read_u32(target, SCB_BASE|RCC, &rcc); DEBUG("Stellaris RCC %x",rcc); @@ -302,7 +317,7 @@ u32 stellaris_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout) int stellaris_flash_command(struct flash_bank_s *bank,u8 cmd,u16 pagen) { u32 fmc; - stellaris_flash_bank_t *stellaris_info = bank->driver_priv; +// stellaris_flash_bank_t *stellaris_info = bank->driver_priv; target_t *target = bank->target; fmc = FMC_WRKEY | cmd; @@ -336,8 +351,7 @@ int stellaris_read_part_info(struct flash_bank_s *bank) if((ver != 0) && (ver != 1)) { WARNING("Unknown did0 version, cannot identify target"); - return ERROR_FLASH_OPERATION_FAILED; - + return ERROR_FLASH_OPERATION_FAILED; } ver = did1 >> 28; @@ -363,7 +377,7 @@ int stellaris_read_part_info(struct flash_bank_s *bank) stellaris_info->did0 = did0; stellaris_info->did1 = did1; - + stellaris_info->num_lockbits = 1+stellaris_info->dc0&0xFFFF; stellaris_info->num_pages = 2*(1+stellaris_info->dc0&0xFFFF); stellaris_info->pagesize = 1024; @@ -376,8 +390,6 @@ int stellaris_read_part_info(struct flash_bank_s *bank) status = stellaris_get_flash_status(bank); - WARNING("stellaris flash only tested for LM3S811 series"); - return ERROR_OK; } @@ -387,11 +399,13 @@ int stellaris_read_part_info(struct flash_bank_s *bank) int stellaris_erase_check(struct flash_bank_s *bank) { + /* + stellaris_flash_bank_t *stellaris_info = bank->driver_priv; target_t *target = bank->target; int i; - /* */ + */ return ERROR_OK; } @@ -401,7 +415,6 @@ int stellaris_protect_check(struct flash_bank_s *bank) u32 status; stellaris_flash_bank_t *stellaris_info = bank->driver_priv; - target_t *target = bank->target; if (stellaris_info->did1 == 0) { @@ -511,7 +524,7 @@ int stellaris_erase(struct flash_bank_s *bank, int first, int last) int stellaris_protect(struct flash_bank_s *bank, int set, int first, int last) { - u32 cmd, fmppe, flash_fmc, flash_cris; + u32 fmppe, flash_fmc, flash_cris; int lockregion; stellaris_flash_bank_t *stellaris_info = bank->driver_priv; @@ -586,15 +599,18 @@ int stellaris_protect(struct flash_bank_s *bank, int set, int first, int last) u8 stellaris_write_code[] = { -/* Call with : +/* + Call with : r0 = buffer address r1 = destination address r2 = bytecount (in) - endaddr (work) + + Used registers: r3 = pFLASH_CTRL_BASE r4 = FLASHWRITECMD r5 = #1 - r6 = scratch - r7 + r6 = bytes written + r7 = temp reg */ 0x07,0x4B, /* ldr r3,pFLASH_CTRL_BASE */ 0x08,0x4C, /* ldr r4,FLASHWRITECMD */ @@ -622,7 +638,7 @@ u8 stellaris_write_code[] = int stellaris_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 wcount) { - stellaris_flash_bank_t *stellaris_info = bank->driver_priv; +// stellaris_flash_bank_t *stellaris_info = bank->driver_priv; target_t *target = bank->target; u32 buffer_size = 8192; working_area_t *source; @@ -632,8 +648,8 @@ int stellaris_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 armv7m_algorithm_t armv7m_info; int retval; - DEBUG("(bank=%08X buffer=%08X offset=%08X wcount=%08X)", - bank, buffer, offset, wcount); + DEBUG("(bank=%08X buffer=%08X offset=%08X wcount=%08X)", + (unsigned int)bank, (unsigned int)buffer, offset, wcount); /* flash write code */ if (target_alloc_working_area(target, sizeof(stellaris_write_code), &write_algorithm) != ERROR_OK) @@ -647,8 +663,8 @@ int stellaris_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 /* memory buffer */ while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) { - DEBUG("called target_alloc_working_area(target=%08X buffer_size=%08X source=%08X)", - target, buffer_size, source); + DEBUG("called target_alloc_working_area(target=%08X buffer_size=%08X source=%08X)", + (unsigned int)target, buffer_size, (unsigned int)source); buffer_size /= 2; if (buffer_size <= 256) { @@ -720,13 +736,12 @@ int stellaris_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count { stellaris_flash_bank_t *stellaris_info = bank->driver_priv; target_t *target = bank->target; - u32 dst_min_alignment, wcount, bytes_remaining = count; u32 address = offset; - u32 fcr,flash_cris,flash_fmc; + u32 flash_cris,flash_fmc; u32 retval; - DEBUG("(bank=%08X buffer=%08X offset=%08X count=%08X)", - bank, buffer, offset, count); + DEBUG("(bank=%08X buffer=%08X offset=%08X count=%08X)", + (unsigned int)bank, (unsigned int)buffer, offset, count); if (bank->target->state != TARGET_HALTED) { diff --git a/src/target/armv7m.c b/src/target/armv7m.c index 5ab9c104..96864fd1 100644 --- a/src/target/armv7m.c +++ b/src/target/armv7m.c @@ -174,6 +174,33 @@ int armv7m_use_context(target_t *target, enum armv7m_runcontext new_ctx) return ERROR_OK; } +int armv7m_restore_context(target_t *target) +{ + int i; + + /* get pointers to arch-specific information */ + armv7m_common_t *armv7m = target->arch_info; + + DEBUG(" "); + + if (armv7m->pre_restore_context) + armv7m->pre_restore_context(target); + + for (i = ARMV7NUMCOREREGS; i >= 0; i--) + { + if (armv7m->core_cache->reg_list[i].dirty) + { + armv7m->write_core_reg(target, i); + } + } + + if (armv7m->post_restore_context) + armv7m->post_restore_context(target); + + return ERROR_OK; +} + + /* Core state functions */ char enamebuf[32]; char *armv7m_exception_string(int number) @@ -207,7 +234,6 @@ int armv7m_set_core_reg(reg_t *reg, u8 *buf) { armv7m_core_reg_t *armv7m_reg = reg->arch_info; target_t *target = armv7m_reg->target; - armv7m_common_t *armv7m_target = target->arch_info; u32 value = buf_get_u32(buf, 0, 32); if (target->state != TARGET_HALTED) @@ -310,12 +336,8 @@ int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_ (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg; } /* ARMV7M is always in thumb mode, try to make GDB understand this if it does not support this arch */ - //armv7m->core_cache->reg_list[15].value[0] |= 1; armv7m->process_context->reg_list[15].value[0] |= 1; - //armv7m->core_cache->reg_list[ARMV7M_xPSR].value[0] = (1<<5); - //armv7m->process_context->reg_list[ARMV7M_xPSR].value[0] = (1<<5); (*reg_list)[25] = &armv7m->process_context->reg_list[ARMV7M_xPSR]; - //(*reg_list)[25] = &armv7m->process_context->reg_list[ARMV7M_xPSR]; return ERROR_OK; } @@ -358,8 +380,6 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ for (i = 0; i < num_reg_params; i++) { reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0); - //reg_t *reg = register_get_by_name(armv7m->debug_context, reg_params[i].reg_name, 0); - //armv7m_core_reg_t * armv7m_core_reg = reg->arch_info; u32 regvalue; if (!reg) @@ -375,7 +395,6 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ } regvalue = buf_get_u32(reg_params[i].value, 0, 32); - //armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, regvalue); armv7m_set_core_reg(reg, reg_params[i].value); } @@ -431,9 +450,7 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ { if (reg_params[i].direction != PARAM_OUT) { - //reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0); reg_t *reg = register_get_by_name(armv7m->debug_context, reg_params[i].reg_name, 0); - u32 regvalue; if (!reg) { @@ -447,23 +464,10 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ exit(-1); } - armv7m_core_reg_t *armv7m_core_reg = reg->arch_info; - //armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, ®value); - //buf_set_u32(reg_params[i].value, 0, 32, regvalue); buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32)); } } - /* Mark all core registers !! except control !! as valid but dirty */ - /* This will be done by armv7m_use_context in resume function */ - //for (i = 0; i < armv7m->core_cache->num_regs-1; i++) - //{ - // armv7m->core_cache->reg_list[i].dirty = 1; - //} - - // ????armv7m->core_state = core_state; - // ????armv7m->core_mode = core_mode; - return retval; } @@ -488,7 +492,6 @@ reg_cache_t *armv7m_build_reg_cache(target_t *target) { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; - arm_jtag_t *jtag_info = &armv7m->jtag_info; int num_regs = ARMV7NUMCOREREGS; reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); @@ -549,7 +552,7 @@ reg_cache_t *armv7m_build_reg_cache(target_t *target) reg_list[i].arch_info = &arch_info[i]; } - return cache; + return cache; } int armv7m_init_target(struct command_context_s *cmd_ctx, struct target_s *target) @@ -573,7 +576,5 @@ int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m) int armv7m_register_commands(struct command_context_s *cmd_ctx) { - int retval; - return ERROR_OK; } diff --git a/src/target/armv7m.h b/src/target/armv7m.h index 49043e1d..8d06cc65 100644 --- a/src/target/armv7m.h +++ b/src/target/armv7m.h @@ -166,6 +166,7 @@ extern int armv7m_invalidate_core_regs(target_t *target); extern enum armv7m_runcontext armv7m_get_context(target_t *target); extern int armv7m_use_context(target_t *target, enum armv7m_runcontext new_ctx); extern enum armv7m_runcontext armv7m_get_context(target_t *target); +extern int armv7m_restore_context(target_t *target); /* Thumb mode instructions */ diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index bdc8b717..c47fbbf8 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -23,8 +23,6 @@ #include "config.h" #endif -#define USE_SP_REGS - #include "replacements.h" #include "cortex_m3.h" @@ -157,6 +155,7 @@ int cortex_m3_cpsid(target_t *target, u32 IF) int cortex_m3_endreset_event(target_t *target) { int i; + u32 dcb_demcr; /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; @@ -165,7 +164,9 @@ int cortex_m3_endreset_event(target_t *target) cortex_m3_fp_comparator_t *fp_list = cortex_m3->fp_comparator_list; cortex_m3_dwt_comparator_t *dwt_list = cortex_m3->dwt_comparator_list; - DEBUG(" "); + ahbap_read_system_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr); + DEBUG("DCB_DEMCR = 0x%8.8x",dcb_demcr); + /* Enable debug requests */ ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) @@ -191,6 +192,7 @@ int cortex_m3_endreset_event(target_t *target) target_write_u32(target, dwt_list[i].dwt_comparator_address | 0x4, dwt_list[i].mask); target_write_u32(target, dwt_list[i].dwt_comparator_address | 0x8, dwt_list[i].function); } + swjdp_transaction_endcheck(swjdp); /* Make sure working_areas are all free */ target_free_all_working_areas(target); @@ -206,7 +208,6 @@ int cortex_m3_examine_debug_reason(target_t *target) /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */ /* only check the debug reason if we don't know it already */ @@ -283,7 +284,7 @@ int cortex_m3_examine_exception_reason(target_t *target) int cortex_m3_debug_entry(target_t *target) { - int i, irq_is_pending; + int i; u32 xPSR; int retval; @@ -321,13 +322,11 @@ int cortex_m3_debug_entry(target_t *target) /* Now we can load SP core registers */ -#ifdef USE_SP_REGS for (i = ARMV7M_PRIMASK; i < ARMV7NUMCOREREGS; i++) { if (!armv7m->core_cache->reg_list[i].valid) armv7m->read_core_reg(target, i); } -#endif /* Are we in an exception handler */ armv7m->core_mode = (xPSR & 0x1FF) ? ARMV7M_MODE_HANDLER : ARMV7M_MODE_THREAD; @@ -345,37 +344,6 @@ int cortex_m3_debug_entry(target_t *target) return ERROR_OK; } -int cortex_m3_restore_context(target_t *target) -{ - int i; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - - DEBUG(" "); - - if (armv7m->pre_restore_context) - armv7m->pre_restore_context(target); - -#ifdef USE_SP_REGS - for (i = ARMV7NUMCOREREGS; i >= 0; i--) -#else - for (i = ARMV7M_PSP; i >= 0; i--) -#endif - { - if (armv7m->core_cache->reg_list[i].dirty) - { - armv7m->write_core_reg(target, i); - } - } - - if (armv7m->post_restore_context) - armv7m->post_restore_context(target); - - return ERROR_OK; -} - enum target_state cortex_m3_poll(target_t *target) { int retval; @@ -415,7 +383,7 @@ enum target_state cortex_m3_poll(target_t *target) if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) { if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK) - return retval; + return TARGET_UNKNOWN; target_call_event_callbacks(target, TARGET_EVENT_HALTED); } @@ -423,7 +391,7 @@ enum target_state cortex_m3_poll(target_t *target) { DEBUG(" "); if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK) - return retval; + return TARGET_UNKNOWN; target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); } @@ -449,6 +417,35 @@ int cortex_m3_halt(target_t *target) DEBUG("target->state: %s", target_state_strings[target->state]); + if (target->state == TARGET_HALTED) + { + WARNING("target was already halted"); + return ERROR_TARGET_ALREADY_HALTED; + } + + if (target->state == TARGET_UNKNOWN) + { + WARNING("target was in unknown state when halt was requested"); + } + + if (target->state == TARGET_RESET) + { + if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst) + { + ERROR("can't request a halt while in reset if nSRST pulls nTRST"); + return ERROR_TARGET_FAILURE; + } + else + { + /* we came here in a reset_halt or reset_init sequence + * debug entry was already prepared in cortex_m3_prepare_reset_halt() + */ + target->debug_reason = DBG_REASON_DBGRQ; + + return ERROR_OK; + } + } + /* Write to Debug Halting Control and Status Register */ ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT ); @@ -510,14 +507,19 @@ int cortex_m3_prepare_reset_halt(struct target_s *target) armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - + u32 dcb_demcr, dcb_dhcsr; + /* Enable debug requests */ ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN ); /* Enter debug state on reset, cf. end_reset_event() */ - ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET ); + ahbap_write_system_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET ); + + ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr); + ahbap_read_system_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr); + DEBUG("dcb_dhcsr 0x%x, dcb_demcr 0x%x, ", dcb_dhcsr, dcb_demcr); return ERROR_OK; } @@ -584,7 +586,7 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand resume_pc = buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32); - cortex_m3_restore_context(target); + armv7m_restore_context(target); /* the front-end may request us not to handle breakpoints */ if (handle_breakpoints) @@ -658,7 +660,7 @@ int cortex_m3_step(struct target_s *target, int current, u32 address, int handle target->debug_reason = DBG_REASON_SINGLESTEP; - cortex_m3_restore_context(target); + armv7m_restore_context(target); target_call_event_callbacks(target, TARGET_EVENT_RESUMED); @@ -1269,7 +1271,7 @@ void cortex_m3_build_reg_cache(target_t *target) int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *target) { - u32 did1, dc0, cpuid, fpcr, dwtcr, ictr; + u32 cpuid, fpcr, dwtcr, ictr; int i; /* get pointers to arch-specific information */ @@ -1333,8 +1335,6 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, in armv7m_common_t *armv7m; armv7m = &cortex_m3->armv7m; - arm_jtag_t *jtag_info = &cortex_m3->jtag_info; - /* prepare JTAG information for the new target */ cortex_m3->jtag_info.chain_pos = chain_pos; cortex_m3->jtag_info.scann_size = 4; diff --git a/src/target/cortex_swjdp.c b/src/target/cortex_swjdp.c index 2a2267ff..85a2abc3 100644 --- a/src/target/cortex_swjdp.c +++ b/src/target/cortex_swjdp.c @@ -164,7 +164,7 @@ int scan_inout_check_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u swjdp_scan_u32(swjdp->jtag_info, SWJDP_IR_DPACC, 0xC, DPAP_READ, 0, invalue, &swjdp->ack); } - /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */ + /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */ if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) { return swjdp_transaction_endcheck(swjdp); @@ -178,6 +178,7 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) int waitcount = 0; u32 ctrlstat; + scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); jtag_execute_queue(); @@ -191,6 +192,7 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) if (waitcount > 100) { WARNING("Timeout waiting for ACK = OK/FAULT in SWJDP transaction"); + return ERROR_JTAG_DEVICE_ERROR; } } @@ -199,6 +201,7 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) WARNING("Invalid ACK in SWJDP transaction"); return ERROR_JTAG_DEVICE_ERROR; } + scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); jtag_execute_queue(); swjdp->ack = swjdp->ack & 0x7; @@ -418,7 +421,7 @@ int ahbap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) count = count - 4 * wcount; while (wcount > 0) { - /* Adjust to read within 4K block boundaries */ + /* Adjust to write blocks within 4K aligned boundaries */ blocksize = (0x1000 - (0xFFF & address)) >> 2; if (wcount < blocksize) blocksize = wcount; @@ -439,7 +442,7 @@ int ahbap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) } if (errorcount > 1) { - WARNING("Block read error address 0x%x, count 0x%x", address, count); + WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount); return ERROR_JTAG_DEVICE_ERROR; } } @@ -573,7 +576,7 @@ int ahbap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address int ahbap_block_read_u32(swjdp_common_t *swjdp, u32 *buffer, int count, u32 address) { int readcount, errorcount = 0; - u32 blockmax, blocksize; + u32 blocksize; swjdp->trans_mode = TRANS_MODE_COMPOSITE; diff --git a/src/target/target.c b/src/target/target.c index de71b140..71ad1e42 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -862,7 +862,7 @@ int target_register_user_commands(struct command_context_s *cmd_ctx) register_command(cmd_ctx, NULL, "wait_halt", handle_wait_halt_command, COMMAND_EXEC, "wait for target halt [time (s)]"); register_command(cmd_ctx, NULL, "halt", handle_halt_command, COMMAND_EXEC, "halt target"); register_command(cmd_ctx, NULL, "resume", handle_resume_command, COMMAND_EXEC, "resume target [addr]"); - register_command(cmd_ctx, NULL, "step", handle_step_command, COMMAND_EXEC, "step one instruction"); + register_command(cmd_ctx, NULL, "step", handle_step_command, COMMAND_EXEC, "step one instruction from current PC or [addr]"); register_command(cmd_ctx, NULL, "reset", handle_reset_command, COMMAND_EXEC, "reset target [run|halt|init|run_and_halt|run_and_init]"); register_command(cmd_ctx, NULL, "soft_reset_halt", handle_soft_reset_halt_command, COMMAND_EXEC, "halt the target and do a soft reset");