From: Minghuan Lian <Minghuan.Lian@nxp.com>
Date: Tue, 13 Dec 2016 06:54:13 +0000 (+0800)
Subject: armv8: ls1043a: add PCIe dts node
X-Git-Tag: v2017.03-rc1~93^2~43
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=ed9bddefb904c3d46bb0dd2e06bcfb082c666579;p=u-boot

armv8: ls1043a: add PCIe dts node

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
---

diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index f038f96171..fe6698f161 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -236,5 +236,51 @@
 			interrupts = <0 63 0x4>;
 			dr_mode = "host";
 		};
+
+		pcie@3400000 {
+			compatible = "fsl,ls-pcie", "snps,dw-pcie";
+			reg = <0x00 0x03400000 0x0 0x10000   /* dbi registers */
+			       0x00 0x03410000 0x0 0x10000   /* lut registers */
+			       0x40 0x00000000 0x0 0x20000>; /* configuration space */
+			reg-names = "dbi", "lut", "config";
+			big-endian;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+		};
+
+		pcie@3500000 {
+			compatible = "fsl,ls-pcie", "snps,dw-pcie";
+			reg = <0x00 0x03500000 0x0 0x10000   /* dbi registers */
+			       0x00 0x03510000 0x0 0x10000   /* lut registers */
+			       0x48 0x00000000 0x0 0x20000>; /* configuration space */
+			reg-names = "dbi", "lut", "config";
+			big-endian;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			num-lanes = <2>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+		};
+
+		pcie@3600000 {
+			compatible = "fsl,ls-pcie", "snps,dw-pcie";
+			reg = <0x00 0x03600000 0x0 0x10000   /* dbi registers */
+			       0x00 0x03610000 0x0 0x10000   /* lut registers */
+			       0x50 0x00000000 0x0 0x20000>; /* configuration space */
+			reg-names = "dbi", "lut", "config";
+			big-endian;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+		};
 	};
 };