From: Lokesh Vutla Date: Wed, 3 Jun 2015 11:27:47 +0000 (+0530) Subject: ARM: DRA7xx: EMIF: Fix DLL_CALIB_CTRL register X-Git-Tag: v2015.07-rc3~79 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=ee4dc2590f00d0109bcdb282ad86fd3dce567e50;p=u-boot ARM: DRA7xx: EMIF: Fix DLL_CALIB_CTRL register When DLL_CALIB_INTERVAL is set, an extra delay is added which is not required and it consumes EMIF bandwidth. So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0. Signed-off-by: Lokesh Vutla --- diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 3022b9e06e..cf4452d260 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -146,7 +146,7 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = { .sdram_tim1 = 0xCCCF36B3, .sdram_tim2 = 0x308F7FDA, .sdram_tim3 = 0x027F88A8, - .read_idle_ctrl = 0x00050001, + .read_idle_ctrl = 0x00050000, .zq_config = 0x0007190B, .temp_alert_config = 0x00000000, .emif_ddr_phy_ctlr_1_init = 0x0024400B, @@ -171,7 +171,7 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = { .sdram_tim1 = 0xCCCF36B3, .sdram_tim2 = 0x308F7FDA, .sdram_tim3 = 0x027F88A8, - .read_idle_ctrl = 0x00050001, + .read_idle_ctrl = 0x00050000, .zq_config = 0x0007190B, .temp_alert_config = 0x00000000, .emif_ddr_phy_ctlr_1_init = 0x0024400B, diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c index 124a1d3ff1..f25e75edda 100644 --- a/board/ti/beagle_x15/board.c +++ b/board/ti/beagle_x15/board.c @@ -52,7 +52,7 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { .sdram_tim1 = 0xceef266b, .sdram_tim2 = 0x328f7fda, .sdram_tim3 = 0x027f88a8, - .read_idle_ctrl = 0x00050001, + .read_idle_ctrl = 0x00050000, .zq_config = 0x0007190b, .temp_alert_config = 0x00000000, .emif_ddr_phy_ctlr_1_init = 0x0024400b, @@ -120,7 +120,7 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { .sdram_tim1 = 0xceef266b, .sdram_tim2 = 0x328f7fda, .sdram_tim3 = 0x027f88a8, - .read_idle_ctrl = 0x00050001, + .read_idle_ctrl = 0x00050000, .zq_config = 0x0007190b, .temp_alert_config = 0x00000000, .emif_ddr_phy_ctlr_1_init = 0x0024400b,