From: Sven Oliver Moll <svolli@svolli.de>
Date: Tue, 6 Sep 2016 12:54:21 +0000 (+0200)
Subject: added README for test/assembler
X-Git-Tag: V2.16~69^2
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=f007fc13d581c0056695e7854d8f9e580f4c2b7c;p=cc65

added README for test/assembler
---

diff --git a/test/assembler/Makefile b/test/assembler/Makefile
index 5e4d580b5..47f403469 100644
--- a/test/assembler/Makefile
+++ b/test/assembler/Makefile
@@ -14,7 +14,7 @@ TARGETS += huc6280
 all: $(addprefix $(WORKDIR)/, $(addsuffix -opcodes.bin, $(TARGETS)))
 	@#
 
-.PHONY: $(addprefix $(WORKDIR)/, $(addsuffix -opcodes.bin, $(TARGETS)))
+.PHONY: all clean $(addprefix $(WORKDIR)/, $(addsuffix -opcodes.bin, $(TARGETS)))
 
 clean:
 	rm -f *.o *.bin *.lst
diff --git a/test/assembler/README b/test/assembler/README
new file mode 100644
index 000000000..697c24449
--- /dev/null
+++ b/test/assembler/README
@@ -0,0 +1,29 @@
+
+Assembler Testcases
+===================
+
+These testcases are inspired by the ones now removed from test/assembler.
+The main purpose is to have each possible opcode generated at least once,
+either by an assembly instruction or a ".byte"-placeholder. Typically
+generated by disassembling a binary dump that contains data in the form
+of the pattern that each opcode is stated once in order followed by easy
+to recognise:
+
+00 00 EA 00
+01 00 EA 00
+02 00 EA 00
+[...]
+fe 00 EA 00
+ff 00 EA 00
+
+The disassembly is then put in a better readable form by replacing the
+leftover dummy opcode parameters with something more recognizable.
+
+The testcases for 6502, 6502x, 65sc02, 65c02, 4510, and huc6280 have been
+put together by Sven Oliver ("SvOlli") Moll, as well as a template for the
+m740 instructions set.
+
+Still to do is to find a way to implement a testcase for the 65816
+processor, since it's capable of executing instructions with an 8-bit and
+a 16-bit operator alike, only distinguished by one processor flag.
+