From: Adam Ford Date: Tue, 8 Aug 2017 14:00:27 +0000 (-0500) Subject: OMAP3: omap3logic: Fix DDR Pin Mux X-Git-Tag: v2017.09-rc2~85 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=f07515578be131a71773f836b761cf135527c2dc;p=u-boot OMAP3: omap3logic: Fix DDR Pin Mux The 512 MB DDR version of SOM's use CS0 and CS1. CS1 is not correctly setup in the pin muxing. This causes erratic behavior on suspend/resume This fix has been tested on both 256 and 512 MB DDR versions. Signed-off-by: Adam Ford --- diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index 7990dd2513..f8b9f687fb 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -320,7 +320,7 @@ void set_muxconf_regs(void) MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)); /*SDRC_CKE1*/ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/