From: Marek Vasut Date: Mon, 8 Jan 2018 15:05:28 +0000 (+0100) Subject: clk: renesas: Make clk_ids per-driver X-Git-Tag: v2018.03-rc1~76^2~34 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=f11c9679aba16e73136e970a6c479751d2f442a1;p=u-boot clk: renesas: Make clk_ids per-driver Not all drivers use the same IDs, so make those IDs per-driver. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index d8576a33ae..647e8e1d9c 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -192,7 +192,8 @@ static int gen3_clk_get_mod(struct clk *clk, const struct mssr_mod_clk **mssr) return -EINVAL; for (i = 0; i < info->mod_clk_size; i++) { - if (info->mod_clk[i].id != MOD_CLK_ID(clkid)) + if (info->mod_clk[i].id != + (info->mod_clk_base + MOD_CLK_PACK(clkid))) continue; *mssr = &info->mod_clk[i]; @@ -322,6 +323,7 @@ static int gen3_clk_disable(struct clk *clk) static ulong gen3_clk_get_rate(struct clk *clk) { struct gen3_clk_priv *priv = dev_get_priv(clk->dev); + struct cpg_mssr_info *info = priv->info; struct clk parent; const struct cpg_core_clk *core; const struct rcar_gen3_cpg_pll_config *pll_config = @@ -350,14 +352,14 @@ static ulong gen3_clk_get_rate(struct clk *clk) switch (core->type) { case CLK_TYPE_IN: - if (core->id == CLK_EXTAL) { + if (core->id == info->clk_extal_id) { rate = clk_get_rate(&priv->clk_extal); debug("%s[%i] EXTAL clk: rate=%u\n", __func__, __LINE__, rate); return rate; } - if (core->id == CLK_EXTALR) { + if (core->id == info->clk_extalr_id) { rate = clk_get_rate(&priv->clk_extalr); debug("%s[%i] EXTALR clk: rate=%u\n", __func__, __LINE__, rate); diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index 58eb073201..ecbb9b31de 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -19,6 +19,36 @@ #include "renesas-cpg-mssr.h" +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R8A7795_CLK_S0D12, + + /* External Input Clocks */ + CLK_EXTAL, + CLK_EXTALR, + + /* Internal Core Clocks */ + CLK_MAIN, + CLK_PLL0, + CLK_PLL1, + CLK_PLL2, + CLK_PLL3, + CLK_PLL4, + CLK_PLL1_DIV2, + CLK_PLL1_DIV4, + CLK_S0, + CLK_S1, + CLK_S2, + CLK_S3, + CLK_SDSRC, + CLK_RPCSRC, + CLK_SSPSRC, + CLK_RINT, + + /* Module Clocks */ + MOD_CLK_BASE +}; + static const struct cpg_core_clk r8a7795_core_clks[] = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), @@ -252,6 +282,9 @@ static const struct cpg_mssr_info r8a7795_cpg_mssr_info = { .mstp_table_size = ARRAY_SIZE(r8a7795_mstp_table), .reset_node = "renesas,r8a7795-rst", .extalr_node = "extalr", + .mod_clk_base = MOD_CLK_BASE, + .clk_extal_id = CLK_EXTAL, + .clk_extalr_id = CLK_EXTALR, }; static const struct udevice_id r8a7795_clk_ids[] = { diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index de1b018b61..6da3b14166 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -19,6 +19,36 @@ #include "renesas-cpg-mssr.h" +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R8A7796_CLK_OSC, + + /* External Input Clocks */ + CLK_EXTAL, + CLK_EXTALR, + + /* Internal Core Clocks */ + CLK_MAIN, + CLK_PLL0, + CLK_PLL1, + CLK_PLL2, + CLK_PLL3, + CLK_PLL4, + CLK_PLL1_DIV2, + CLK_PLL1_DIV4, + CLK_S0, + CLK_S1, + CLK_S2, + CLK_S3, + CLK_SDSRC, + CLK_RPCSRC, + CLK_SSPSRC, + CLK_RINT, + + /* Module Clocks */ + MOD_CLK_BASE +}; + static const struct cpg_core_clk r8a7796_core_clks[] = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), @@ -225,6 +255,9 @@ static const struct cpg_mssr_info r8a7796_cpg_mssr_info = { .mstp_table_size = ARRAY_SIZE(r8a7796_mstp_table), .reset_node = "renesas,r8a7796-rst", .extalr_node = "extalr", + .mod_clk_base = MOD_CLK_BASE, + .clk_extal_id = CLK_EXTAL, + .clk_extalr_id = CLK_EXTALR, }; static const struct udevice_id r8a7796_clk_ids[] = { diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c index 28d9459285..fe36b11f7e 100644 --- a/drivers/clk/renesas/r8a77970-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c @@ -19,6 +19,41 @@ #include "renesas-cpg-mssr.h" +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R8A77970_CLK_OSC, + + /* External Input Clocks */ + CLK_EXTAL, + CLK_EXTALR, + + /* Internal Core Clocks */ + CLK_MAIN, + CLK_PLL0, + CLK_PLL1, + CLK_PLL2, + CLK_PLL3, + CLK_PLL4, + CLK_PLL1_DIV2, + CLK_PLL1_DIV4, + CLK_PLL0D2, + CLK_PLL0D3, + CLK_PLL0D5, + CLK_PLL1D2, + CLK_PE, + CLK_S0, + CLK_S1, + CLK_S2, + CLK_S3, + CLK_SDSRC, + CLK_RPCSRC, + CLK_SSPSRC, + CLK_RINT, + + /* Module Clocks */ + MOD_CLK_BASE +}; + static const struct cpg_core_clk r8a77970_core_clks[] = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), @@ -128,6 +163,9 @@ static const struct cpg_mssr_info r8a77970_cpg_mssr_info = { .mstp_table_size = ARRAY_SIZE(r8a77970_mstp_table), .reset_node = "renesas,r8a77970-rst", .extalr_node = "extalr", + .mod_clk_base = MOD_CLK_BASE, + .clk_extal_id = CLK_EXTAL, + .clk_extalr_id = CLK_EXTALR, }; static const struct udevice_id r8a77970_clk_ids[] = { diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c index a4e289e329..c754c1356f 100644 --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c @@ -19,6 +19,34 @@ #include "renesas-cpg-mssr.h" +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R8A77995_CLK_CP, + + /* External Input Clocks */ + CLK_EXTAL, + + /* Internal Core Clocks */ + CLK_MAIN, + CLK_PLL0, + CLK_PLL1, + CLK_PLL3, + CLK_PLL0D2, + CLK_PLL0D3, + CLK_PLL0D5, + CLK_PLL1D2, + CLK_PE, + CLK_S0, + CLK_S1, + CLK_S2, + CLK_S3, + CLK_SDSRC, + CLK_SSPSRC, + + /* Module Clocks */ + MOD_CLK_BASE +}; + static const struct cpg_core_clk r8a77995_core_clks[] = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), @@ -158,6 +186,9 @@ static const struct cpg_mssr_info r8a77995_cpg_mssr_info = { .mstp_table = r8a77995_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a77995_mstp_table), .reset_node = "renesas,r8a77995-rst", + .mod_clk_base = MOD_CLK_BASE, + .clk_extal_id = CLK_EXTAL, + .clk_extalr_id = ~0, }; static const struct udevice_id r8a77995_clk_ids[] = { diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index 4e1e45ff45..2303baa1fd 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -23,6 +23,9 @@ struct cpg_mssr_info { unsigned int mstp_table_size; const char *reset_node; const char *extalr_node; + unsigned int mod_clk_base; + unsigned int clk_extal_id; + unsigned int clk_extalr_id; }; struct gen3_clk_priv { @@ -117,43 +120,6 @@ struct rcar_gen3_cpg_pll_config { unsigned int pll3_mult; }; -#include - -enum clk_ids { - /* Core Clock Outputs exported to DT */ - LAST_DT_CORE_CLK = R8A7796_CLK_OSC, - - /* External Input Clocks */ - CLK_EXTAL, - CLK_EXTALR, - - /* Internal Core Clocks */ - CLK_MAIN, - CLK_PLL0, - CLK_PLL1, - CLK_PLL2, - CLK_PLL3, - CLK_PLL4, - CLK_PLL1_DIV2, - CLK_PLL1_DIV4, - CLK_PLL0D2, - CLK_PLL0D3, - CLK_PLL0D5, - CLK_PLL1D2, - CLK_PE, - CLK_S0, - CLK_S1, - CLK_S2, - CLK_S3, - CLK_SDSRC, - CLK_RPCSRC, - CLK_SSPSRC, - CLK_RINT, - - /* Module Clocks */ - MOD_CLK_BASE -}; - struct mstp_stop_table { u32 dis; u32 en;