From: Antony Pavlov Date: Tue, 7 Oct 2014 08:36:55 +0000 (+0400) Subject: mips32: fix typos X-Git-Tag: v0.9.0-rc1~224 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=f16b7a6d7e4464692c7fcd8d39e150a09c270d1b;p=openocd mips32: fix typos Change-Id: Ibb98fe3da68bf670a5bb83600bb49647db8a4163 Signed-off-by: Antony Pavlov Reviewed-on: http://openocd.zylin.com/2338 Tested-by: jenkins Reviewed-by: Spencer Oliver --- diff --git a/src/target/mips32.c b/src/target/mips32.c index d842705f..75197f17 100644 --- a/src/target/mips32.c +++ b/src/target/mips32.c @@ -289,7 +289,7 @@ int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, s mips32->common_magic = MIPS32_COMMON_MAGIC; mips32->fast_data_area = NULL; - /* has breakpoint/watchpint unit been scanned */ + /* has breakpoint/watchpoint unit been scanned */ mips32->bp_scanned = 0; mips32->data_break_list = NULL; diff --git a/src/target/mips32.h b/src/target/mips32.h index 951b2ed7..4f44384a 100644 --- a/src/target/mips32.h +++ b/src/target/mips32.h @@ -203,7 +203,7 @@ struct mips32_algorithm { #define MIPS32_SYNCI_STEP 0x1 /* reg num od address step size to be used with synci instruction */ /** - * Cache operations definietions + * Cache operations definitions * Operation field is 5 bits long : * 1) bits 1..0 hold cache type * 2) bits 4..2 hold operation code