From: Masahiro Yamada <yamada.m@jp.panasonic.com>
Date: Thu, 26 Feb 2015 17:26:50 +0000 (+0900)
Subject: ARM: UniPhier: rename SC_CLKCTRL_CLK_* to SC_SCLKCTRL_CEN_*
X-Git-Tag: v2015.04-rc3~11^2~16
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=f267b81e20da095539c7da7103afbd1e1b39b20b;p=u-boot

ARM: UniPhier: rename SC_CLKCTRL_CLK_* to SC_SCLKCTRL_CEN_*

Follow the register macros in the LSI specification book.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
---

diff --git a/arch/arm/mach-uniphier/include/mach/sc-regs.h b/arch/arm/mach-uniphier/include/mach/sc-regs.h
index 1197bb52d4..7726530f0b 100644
--- a/arch/arm/mach-uniphier/include/mach/sc-regs.h
+++ b/arch/arm/mach-uniphier/include/mach/sc-regs.h
@@ -47,12 +47,12 @@
 #define SC_RSTCTRL3			(SC_BASE_ADDR | 0x2008)
 
 #define SC_CLKCTRL			(SC_BASE_ADDR | 0x2104)
-#define SC_CLKCTRL_CLK_ETHER		(0x1 << 12)
-#define SC_CLKCTRL_CLK_MIO		(0x1 << 11)
-#define SC_CLKCTRL_CLK_UMC		(0x1 <<  4)
-#define SC_CLKCTRL_CLK_NAND		(0x1 <<  2)
-#define SC_CLKCTRL_CLK_SBC		(0x1 <<  1)
-#define SC_CLKCTRL_CLK_PERI		(0x1 <<  0)
+#define SC_CLKCTRL_CEN_ETHER		(0x1 << 12)
+#define SC_CLKCTRL_CEN_MIO		(0x1 << 11)
+#define SC_CLKCTRL_CEN_UMC		(0x1 <<  4)
+#define SC_CLKCTRL_CEN_NAND		(0x1 <<  2)
+#define SC_CLKCTRL_CEN_SBC		(0x1 <<  1)
+#define SC_CLKCTRL_CEN_PERI		(0x1 <<  0)
 
 /* System reset control register */
 #define SC_IRQTIMSET			(SC_BASE_ADDR | 0x3000)
diff --git a/arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c b/arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c
index 6a9d144f82..eaa45f94d3 100644
--- a/arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c
+++ b/arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c
@@ -22,8 +22,8 @@ void clkrst_init(void)
 
 	/* privide clocks */
 	tmp = readl(SC_CLKCTRL);
-	tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
-	     | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
+	tmp |= SC_CLKCTRL_CEN_ETHER | SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_UMC
+	     | SC_CLKCTRL_CEN_NAND | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
 	writel(tmp, SC_CLKCTRL);
 	readl(SC_CLKCTRL); /* dummy read */
 }
diff --git a/arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c b/arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c
index 6a9d144f82..eaa45f94d3 100644
--- a/arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c
+++ b/arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c
@@ -22,8 +22,8 @@ void clkrst_init(void)
 
 	/* privide clocks */
 	tmp = readl(SC_CLKCTRL);
-	tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
-	     | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
+	tmp |= SC_CLKCTRL_CEN_ETHER | SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_UMC
+	     | SC_CLKCTRL_CEN_NAND | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
 	writel(tmp, SC_CLKCTRL);
 	readl(SC_CLKCTRL); /* dummy read */
 }
diff --git a/arch/arm/mach-uniphier/ph1-pro4/lowlevel_debug.S b/arch/arm/mach-uniphier/ph1-pro4/lowlevel_debug.S
index 45aef7ad50..fcaf6d12d8 100644
--- a/arch/arm/mach-uniphier/ph1-pro4/lowlevel_debug.S
+++ b/arch/arm/mach-uniphier/ph1-pro4/lowlevel_debug.S
@@ -17,7 +17,7 @@
 ENTRY(setup_lowlevel_debug)
 		ldr		r0, =SC_CLKCTRL
 		ldr		r1, [r0]
-		orr		r1, r1, #SC_CLKCTRL_CLK_PERI
+		orr		r1, r1, #SC_CLKCTRL_CEN_PERI
 		str		r1, [r0]
 
 		init_debug_uart	r0, r1, r2
diff --git a/arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c b/arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c
index 6a9d144f82..eaa45f94d3 100644
--- a/arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c
+++ b/arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c
@@ -22,8 +22,8 @@ void clkrst_init(void)
 
 	/* privide clocks */
 	tmp = readl(SC_CLKCTRL);
-	tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
-	     | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
+	tmp |= SC_CLKCTRL_CEN_ETHER | SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_UMC
+	     | SC_CLKCTRL_CEN_NAND | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
 	writel(tmp, SC_CLKCTRL);
 	readl(SC_CLKCTRL); /* dummy read */
 }