From: Stefan Roese <sr@denx.de>
Date: Mon, 27 Jul 2009 08:53:43 +0000 (+0200)
Subject: ppc4xx: Fix Arches DDR2 initialization
X-Git-Tag: v2009.08-rc2~41^2~3
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=f3ed3c9b7441cde936d06a1ff7b1490ff0d600e6;p=u-boot

ppc4xx: Fix Arches DDR2 initialization

Testing on AMCC Arches with the latest U-Boot version yielded that DDR2
initialization is currently broken. U-Boot hangs upon relocation to SDRAM
or crashes with random traps. This patch fixes this problem. Arches now
uses a different WRDTR and CLKTR default setting than Canyonlands/Glacier.

Signed-off-by: Stefan Roese <sr@denx.de>
---

diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index cfc1023f4f..c0c135201f 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -40,6 +40,24 @@ DECLARE_GLOBAL_DATA_PTR;
 #define BOARD_GLACIER		3
 #define BOARD_ARCHES		4
 
+/*
+ * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ */
+#if defined(CONFIG_ARCHES)
+u32 ddr_wrdtr(u32 default_val) {
+	return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_0_DEG | 0x823);
+}
+#else
+u32 ddr_wrdtr(u32 default_val) {
+	return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
+}
+
+u32 ddr_clktr(u32 default_val) {
+	return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
+}
+#endif
+
 #if defined(CONFIG_ARCHES)
 /*
  * FPGA read/write helper macros
@@ -286,18 +304,6 @@ int checkboard(void)
 }
 #endif	/* !defined(CONFIG_ARCHES) */
 
-/*
- * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
- * board specific values.
- */
-u32 ddr_wrdtr(u32 default_val) {
-	return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
-}
-
-u32 ddr_clktr(u32 default_val) {
-	return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
-}
-
 #if defined(CONFIG_NAND_U_BOOT)
 /*
  * NAND booting U-Boot version uses a fixed initialization, since the whole