From: Stephen Warren <swarren@nvidia.com>
Date: Tue, 24 Feb 2015 21:08:30 +0000 (-0700)
Subject: ARM: tegra: pinmux: support Tegra210's e_io_hv pin option
X-Git-Tag: v2015.04-rc4~31^2~5
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=f4d7c9dd443b7c736304dd2b80b82a7b6074a25a;p=u-boot

ARM: tegra: pinmux: support Tegra210's e_io_hv pin option

Tegra210 has a per-pin option named e_io_hv, which indicates that the
pin's input path should be configured to be 3.3v-tolerant. Add support
for this.

Note that this is very similar to previous chip's rcv_sel option.
However, since the Tegra TRM names this option differently for the
different chips, we support the new name so that the code exactly matches
the naming in the TRM, to avoid confusion.

This patch incorporates a few fixes from Tom Warren <twarren@nvidia.com>.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---

diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h
index d87da10e0d..4212e57699 100644
--- a/arch/arm/include/asm/arch-tegra/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra/pinmux.h
@@ -63,6 +63,14 @@ enum pmux_pin_rcv_sel {
 };
 #endif
 
+#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
+enum pmux_pin_e_io_hv {
+	PMUX_PIN_E_IO_HV_DEFAULT = 0,
+	PMUX_PIN_E_IO_HV_NORMAL,
+	PMUX_PIN_E_IO_HV_HIGH,
+};
+#endif
+
 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
 /* Defines a pin group cfg's low-power mode select */
 enum pmux_lpmd {
@@ -119,6 +127,9 @@ struct pmux_pingrp_config {
 	u32 rcv_sel:2;		/* select between High and Normal  */
 				/* VIL/VIH receivers */
 #endif
+#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
+	u32 e_io_hv:2;		/* select 3.3v tolerant receivers */
+#endif
 #ifdef TEGRA_PMX_PINS_HAVE_SCHMT
 	u32 schmt:2;		/* schmitt enable            */
 #endif
diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c
index 9bf3086971..912f65e98b 100644
--- a/arch/arm/mach-tegra/pinmux-common.c
+++ b/arch/arm/mach-tegra/pinmux-common.c
@@ -56,6 +56,13 @@
 	 ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
 #endif
 
+#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
+/* return 1 if a pin_e_io_hv is in range */
+#define pmux_pin_e_io_hv_isvalid(e_io_hv) \
+	(((e_io_hv) >= PMUX_PIN_E_IO_HV_NORMAL) && \
+	 ((e_io_hv) <= PMUX_PIN_E_IO_HV_HIGH))
+#endif
+
 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
 #define pmux_lpmd_isvalid(lpm) \
 	(((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
@@ -113,6 +120,7 @@
 #ifdef TEGRA_PMX_PINS_HAVE_HSM
 #define HSM_SHIFT	9
 #endif
+#define E_IO_HV_SHIFT	10
 #define OD_SHIFT	11
 #ifdef TEGRA_PMX_PINS_HAVE_SCHMT
 #define SCHMT_SHIFT	12
@@ -342,6 +350,31 @@ static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
 }
 #endif
 
+#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
+static void pinmux_set_e_io_hv(enum pmux_pingrp pin,
+				enum pmux_pin_e_io_hv e_io_hv)
+{
+	u32 *reg = REG(pin);
+	u32 val;
+
+	if (e_io_hv == PMUX_PIN_E_IO_HV_DEFAULT)
+		return;
+
+	/* Error check on pin and e_io_hv */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_e_io_hv_isvalid(e_io_hv));
+
+	val = readl(reg);
+	if (e_io_hv == PMUX_PIN_E_IO_HV_HIGH)
+		val |= (1 << E_IO_HV_SHIFT);
+	else
+		val &= ~(1 << E_IO_HV_SHIFT);
+	writel(val, reg);
+
+	return;
+}
+#endif
+
 #ifdef TEGRA_PMX_PINS_HAVE_SCHMT
 static void pinmux_set_schmt(enum pmux_pingrp pin, enum pmux_schmt schmt)
 {
@@ -414,6 +447,9 @@ static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
 	pinmux_set_rcv_sel(pin, config->rcv_sel);
 #endif
+#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
+	pinmux_set_e_io_hv(pin, config->e_io_hv);
+#endif
 #ifdef TEGRA_PMX_PINS_HAVE_SCHMT
 	pinmux_set_schmt(pin, config->schmt);
 #endif