From: Vaibhav Hiremath Date: Sun, 4 Sep 2011 01:29:59 +0000 (-0400) Subject: omap3:clock: configure GFX clock to 200MHz for AM/DM37x X-Git-Tag: v2011.09-rc1~68^2~53 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=f4dac3e16c1a08eb087e711a7e0ada3cf390d7ea;p=u-boot omap3:clock: configure GFX clock to 200MHz for AM/DM37x AM/DM37x is another OMAP3 variant, where the GFX clock has been boosted to 192MHz/200MHz. So fix the GFX_DIV value for this change. HW Errata: Due to dependency of TV out clock of 54MHz, it is not possible to configure GFX to 192MHz. So as per HW errats, the recommended GFX clock is 200MHz (=CORE_CLK/2). Signed-off-by: Vaibhav Hiremath Signed-off-by: Sandeep Paulraj --- diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index 3d38d08ccb..29ff7131de 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -399,7 +399,7 @@ static void dpll3_init_36xx(u32 sil_index, u32 clk_index) /* L3 */ sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV); /* GFX */ - sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV); + sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV_36X); /* RESET MGR */ sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM); /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ diff --git a/arch/arm/include/asm/arch-omap3/clocks_omap3.h b/arch/arm/include/asm/arch-omap3/clocks_omap3.h index ef600dd9db..db29b7c6df 100644 --- a/arch/arm/include/asm/arch-omap3/clocks_omap3.h +++ b/arch/arm/include/asm/arch-omap3/clocks_omap3.h @@ -39,6 +39,7 @@ #define CORE_L4_DIV 2 /* 83MHz : L4 */ #define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ #define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ +#define GFX_DIV_36X 5 /* 200MHz : CM_CLKSEL_GFX */ #define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ /* PER DPLL */