From: Simon Glass <sjg@chromium.org>
Date: Sun, 17 Jan 2016 23:11:19 +0000 (-0700)
Subject: x86: ivybridge: Probe the LPC in CPU init
X-Git-Tag: v2016.03-rc1~119
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=f633efa30f6119c9cecb045e7edeb01554800d84;p=u-boot

x86: ivybridge: Probe the LPC in CPU init

We can drop the explicit probe of the PCH since the LPC is a child device
and this will happen automatically.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index f32b4a18e1..65eea1f9ee 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -212,7 +212,7 @@ int print_cpuinfo(void)
 {
 	enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE;
 	char processor_name[CPU_MAX_NAME_LEN];
-	struct udevice *dev;
+	struct udevice *dev, *lpc;
 	const char *name;
 	uint32_t pm1_cnt;
 	uint16_t pm1_sts;
@@ -245,12 +245,11 @@ int print_cpuinfo(void)
 	/* Early chipset init required before RAM init can work */
 	uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
 
-	ret = uclass_first_device(UCLASS_PCH, &dev);
+	ret = uclass_first_device(UCLASS_LPC, &lpc);
 	if (ret)
 		return ret;
 	if (!dev)
 		return -ENODEV;
-
 	sandybridge_early_init(SANDYBRIDGE_MOBILE);
 
 	/* Check PM1_STS[15] to see if we are waking from Sx */