From: rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Date: Sun, 30 Dec 2018 23:53:47 +0000 (+0000)
Subject: Re-org of RISC-V file structure and naming step 2.
X-Git-Tag: V10.2.0~22
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=f7fa3e0bc24519d2605efe81d16ece1fbeb5e286;p=freertos

Re-org of RISC-V file structure and naming step 2.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2620 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
---

diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/.cproject b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/.cproject
index b963a9fc9..38177fd60 100644
--- a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/.cproject
+++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/.cproject
@@ -50,7 +50,7 @@
 								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor.874608690" name="Use preprocessor" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths.545620458" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths" useByScannerDiscovery="true" valueType="includePath">
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/freedom-e-sdk/env}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS_Source/portable/GCC/RISC-V-RV32/CLINT_no_extensions}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS_Source/portable/GCC/RISC-V-RV32}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/freedom-e-sdk/include}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/freedom-e-sdk/env/freedom-e300-hifive1}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/freedom-e-sdk/drivers}&quot;"/>
diff --git a/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/.cproject b/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/.cproject
index af593fd3c..9a95c98e7 100644
--- a/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/.cproject
+++ b/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/.cproject
@@ -99,7 +99,7 @@
                                 								
                                 <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths.1792818218" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths" useByScannerDiscovery="true" valueType="includePath">
                                     									
-                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS_Source/portable/GCC/RISC-V-RV32/CLINT_no_extensions}&quot;"/>
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS_Source/portable/GCC/RISC-V-RV32}&quot;"/>
                                     								
                                 </option>
                                 								
diff --git a/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/entry.S b/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/entry.S
index fce18d785..641237004 100644
--- a/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/entry.S
+++ b/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/entry.S
@@ -24,7 +24,7 @@
 #endif
 
   .section      .text.entry
-  .extern vFreeRTOSPortTrapHandler
+  .extern freertos_risc_v_trap_handler
   .globl _start
 
 _start:
@@ -34,10 +34,10 @@ nmi_vector:
   j nmi_vector
 
 trap_vector:
-  j vFreeRTOSPortTrapHandler
+  j freertos_risc_v_trap_handler
 
 handle_reset:
-  la t0, vFreeRTOSPortTrapHandler
+  la t0, freertos_risc_v_trap_handler
   csrw mtvec, t0
   csrwi mstatus, 0
   csrwi mie, 0
diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
new file mode 100644
index 000000000..da213e92f
--- /dev/null
+++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
@@ -0,0 +1,114 @@
+/*
+ * FreeRTOS Kernel V10.1.1
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and t
+
+ o permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
+ *
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ *   is common to all currently supported RISC-V chips.  There is only one
+ *   portASM.S file because the same file is built for all RISC-V target chips.
+ *
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
+ *   code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
+ *   chip.  There are multiple freertos_risc_v_chip_specific_extensions.h files
+ *   as there are multiple RISC-V chip implementations.
+ *
+ * !!!NOTE!!!
+ * CARE MUST BE TAKEN TO INCLUDE THE CORRECT
+ * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP IN USE.
+ * If the chip in use includes a core local interrupter (CLINT) and does not
+ * include any chip specific register extensions then set the GNU assembler's
+ * include path such that the header file contained in the
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32 directory is the header file that is
+ * actually inlcuded.  Otherwise set the assembler's include patch to the
+ * sub-directory off of the
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions directory
+ * that contains the freertos_risc_v_chip_specific_extensions.h specific to the
+ * target chip.
+ *
+ */
+
+/*
+ * This freertos_risc_v_chip_specific_extensions.h is for use with Pulpino Ri5cy
+ * devices, developed and tested using the Vega board RV32M1RM.
+ */
+
+#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
+#define __FREERTOS_RISC_V_EXTENSIONS_H__
+
+#define portasmHAS_CLINT 0
+
+/* Constants to define the additional registers found on the Pulpino RI5KY. */
+#define lpstart0 	0x7b0
+#define lpend0 		0x7b1
+#define lpcount0 	0x7b2
+#define lpstart1 	0x7b4
+#define lpend1 		0x7b5
+#define lpcount1 	0x7b6
+
+/* Six additional registers to save and restore, as per the #defines above. */
+#define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */
+
+/* Save additional registers found on the Pulpino. */
+.macro portasmSAVE_ADDITIONAL_REGISTERS
+	addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */
+	csrr t0, lpstart0							 /* Load additional registers into accessable temporary registers. */
+	csrr t1, lpend0
+	csrr t2, lpcount0
+	csrr t3, lpstart1
+	csrr t4, lpend1
+	csrr t5, lpcount1
+	sw t0, 1 * portWORD_SIZE( sp )
+	sw t1, 2 * portWORD_SIZE( sp )
+	sw t2, 3 * portWORD_SIZE( sp )
+	sw t3, 4 * portWORD_SIZE( sp )
+	sw t4, 5 * portWORD_SIZE( sp )
+	sw t5, 6 * portWORD_SIZE( sp )
+	.endm
+
+/* Restore the additional registers found on the Pulpino. */
+.macro portasmRESTORE_ADDITIONAL_REGISTERS
+	lw t0, 1 * portWORD_SIZE( sp )			/* Load additional registers into accessable temporary registers. */
+	lw t1, 2 * portWORD_SIZE( sp )
+	lw t2, 3 * portWORD_SIZE( sp )
+	lw t3, 4 * portWORD_SIZE( sp )
+	lw t4, 5 * portWORD_SIZE( sp )
+	lw t5, 6 * portWORD_SIZE( sp )
+	csrw lpstart0, t0
+	csrw lpend0, t1
+	csrw lpcount0, t2
+	csrw lpstart1, t3
+	csrw lpend1, t4
+	csrw lpcount1, t5
+	addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE )/* Remove space added for additional registers. */
+	.endm
+
+#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h
deleted file mode 100644
index 5121abab1..000000000
--- a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and t
-
- o permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
- * The FreeRTOS kernel's RISC-V port is split between the the code that is
- * common across all currently supported RISC-V chips (implementations of the
- * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
- *
- * + The code that is common to all RISC-V chips is implemented in
- *   FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S.  There is only one
- *   portASM.S file because the same file is used no matter which RISC-V chip is
- *   in use.
- *
- * + The code that tailors the kernel's RISC-V port to a specific RISC-V
- *   chip is implemented in freertos_risc_v_port_specific_extensions.h.  There
- *   is one freertos_risc_v_port_specific_extensions.h that can be used with any
- *   RISC-V chip that both includes a standard CLINT and does not add to the
- *   base set of RISC-V registers.  There are additional
- *   freertos_risc_v_port_specific_extensions.h files for RISC-V implementations
- *   that do not include a standard CLINT or do add to the base set of RISC-V
- *   registers.
- *
- * CARE MUST BE TAKEN TO INCLDUE THE CORRECT
- * freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP
- * IN USE.  To include the correct freertos_risc_v_port_specific_extensions.h
- * header file ensure the path to the correct header file is in the assembler's
- * include path.
- *
- * This freertos_risc_v_port_specific_extensions.h is for use with Pulpino Ri5cy
- * devices, developed and tested using the Vega board RV32M1RM.
- *
- */
-
-#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
-#define __FREERTOS_RISC_V_EXTENSIONS_H__
-
-#define portasmHAS_CLINT 0
-
-/* Constants to define the additional registers found on the Pulpino RI5KY. */
-#define lpstart0 	0x7b0
-#define lpend0 		0x7b1
-#define lpcount0 	0x7b2
-#define lpstart1 	0x7b4
-#define lpend1 		0x7b5
-#define lpcount1 	0x7b6
-
-/* Six additional registers to save and restore, as per the #defines above. */
-#define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */
-
-/* Save additional registers found on the Pulpino. */
-.macro portasmSAVE_ADDITIONAL_REGISTERS
-	addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */
-	csrr t0, lpstart0							 /* Load additional registers into accessable temporary registers. */
-	csrr t1, lpend0
-	csrr t2, lpcount0
-	csrr t3, lpstart1
-	csrr t4, lpend1
-	csrr t5, lpcount1
-	sw t0, 1 * portWORD_SIZE( sp )
-	sw t1, 2 * portWORD_SIZE( sp )
-	sw t2, 3 * portWORD_SIZE( sp )
-	sw t3, 4 * portWORD_SIZE( sp )
-	sw t4, 5 * portWORD_SIZE( sp )
-	sw t5, 6 * portWORD_SIZE( sp )
-	.endm
-
-/* Restore the additional registers found on the Pulpino. */
-.macro portasmRESTORE_ADDITIONAL_REGISTERS
-	lw t0, 1 * portWORD_SIZE( sp )			/* Load additional registers into accessable temporary registers. */
-	lw t1, 2 * portWORD_SIZE( sp )
-	lw t2, 3 * portWORD_SIZE( sp )
-	lw t3, 4 * portWORD_SIZE( sp )
-	lw t4, 5 * portWORD_SIZE( sp )
-	lw t5, 6 * portWORD_SIZE( sp )
-	csrw lpstart0, t0
-	csrw lpend0, t1
-	csrw lpcount0, t2
-	csrw lpstart1, t3
-	csrw lpend1, t4
-	csrw lpcount1, t5
-	addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE )/* Remove space added for additional registers. */
-	.endm
-
-#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/chip_specific_extensions/readme.txt b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/chip_specific_extensions/readme.txt
new file mode 100644
index 000000000..b94a43687
--- /dev/null
+++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/chip_specific_extensions/readme.txt
@@ -0,0 +1,28 @@
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
+ *
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ *   is common to all currently supported RISC-V chips.  There is only one
+ *   portASM.S file because the same file is built for all RISC-V target chips.
+ *
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
+ *   code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
+ *   chip.  There are multiple freertos_risc_v_chip_specific_extensions.h files
+ *   as there are multiple RISC-V chip implementations.
+ *
+ * !!!NOTE!!!
+ * CARE MUST BE TAKEN TO INCLUDE THE CORRECT
+ * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP IN USE.
+ * If the chip in use includes a core local interrupter (CLINT) and does not
+ * include any chip specific register extensions then set the GNU assembler's
+ * include path such that the header file contained in the
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32 directory is the header file that is
+ * actually inlcuded.  Otherwise set the assembler's include patch to the
+ * sub-directory off of the
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions directory
+ * that contains the freertos_risc_v_chip_specific_extensions.h specific to the
+ * target chip.
+ *
+ */
diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/freertos_risc_v_chip_specific_extensions.h b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/freertos_risc_v_chip_specific_extensions.h
new file mode 100644
index 000000000..f911cd96d
--- /dev/null
+++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/freertos_risc_v_chip_specific_extensions.h
@@ -0,0 +1,72 @@
+/*
+ * FreeRTOS Kernel V10.1.1
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
+ *
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ *   is common to all currently supported RISC-V chips.  There is only one
+ *   portASM.S file because the same file is built for all RISC-V target chips.
+ *
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
+ *   code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
+ *   chip.  There are multiple freertos_risc_v_chip_specific_extensions.h files
+ *   as there are multiple RISC-V chip implementations.
+ *
+ * !!!NOTE!!!
+ * CARE MUST BE TAKEN TO INCLUDE THE CORRECT
+ * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP IN USE.
+ * If the chip in use includes a core local interrupter (CLINT) and does not
+ * include any chip specific register extensions then set the GNU assembler's
+ * include path such that the header file contained in the
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32 directory is the header file that is
+ * actually inlcuded.  Otherwise set the assembler's include patch to the
+ * sub-directory off of the
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions directory
+ * that contains the freertos_risc_v_chip_specific_extensions.h specific to the
+ * target chip.
+ *
+ */
+
+#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
+#define __FREERTOS_RISC_V_EXTENSIONS_H__
+
+#define portasmHAS_CLINT 1
+#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */
+
+.macro portasmSAVE_ADDITIONAL_REGISTERS
+	/* No additional registers to save, so this macro does nothing. */
+	.endm
+
+/* Restore the additional registers found on the Pulpino. */
+.macro portasmRESTORE_ADDITIONAL_REGISTERS
+	/* No additional registers to restore, so this macro does nothing. */
+	.endm
+
+#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/freertos_risc_v_port_specific_extensions.h b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/freertos_risc_v_port_specific_extensions.h
deleted file mode 100644
index a5544b061..000000000
--- a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/freertos_risc_v_port_specific_extensions.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and t
-
- o permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
- * The FreeRTOS kernel's RISC-V port is split between the the code that is
- * common across all currently supported RISC-V chips (implementations of the
- * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
- *
- * + The code that is common to all RISC-V chips is implemented in
- *   FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S.  There is only one
- *   portASM.S file because the same file is used no matter which RISC-V chip is
- *   in use.
- *
- * + The code that tailors the kernel's RISC-V port to a specific RISC-V
- *   chip is implemented in freertos_risc_v_port_specific_extensions.h.  There
- *   is one freertos_risc_v_port_specific_extensions.h that can be used with any
- *   RISC-V chip that both includes a standard CLINT and does not add to the
- *   base set of RISC-V registers.  There are additional
- *   freertos_risc_v_port_specific_extensions.h files for RISC-V implementations
- *   that do not include a standard CLINT or do add to the base set of RISC-V
- *   registers.
- *
- * CARE MUST BE TAKEN TO INCLDUE THE CORRECT
- * freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP
- * IN USE.  To include the correct freertos_risc_v_port_specific_extensions.h
- * header file ensure the path to the correct header file is in the assembler's
- * include path.
- *
- * This freertos_risc_v_port_specific_extensions.h is for use on RISC-V chips
- * that include a standard CLINT and do not add to the base set of RISC-V
- * registers.
- *
- */
-
-#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
-#define __FREERTOS_RISC_V_EXTENSIONS_H__
-
-#define portasmHAS_CLINT 1
-#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */
-
-.macro portasmSAVE_ADDITIONAL_REGISTERS
-	/* No additional registers to save, so this macro does nothing. */
-	.endm
-
-/* Restore the additional registers found on the Pulpino. */
-.macro portasmRESTORE_ADDITIONAL_REGISTERS
-	/* No additional registers to restore, so this macro does nothing. */
-	.endm
-
-#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S
index 5d9e5f307..4f3e5a8bb 100644
--- a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S
+++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S
@@ -45,46 +45,46 @@
  *   in use.
  *
  * + The code that tailors the kernel's RISC-V port to a specific RISC-V
- *   chip is implemented in freertos_risc_v_port_specific_extensions.h.  There
- *   is one freertos_risc_v_port_specific_extensions.h that can be used with any
+ *   chip is implemented in freertos_risc_v_chip_specific_extensions.h.  There
+ *   is one freertos_risc_v_chip_specific_extensions.h that can be used with any
  *   RISC-V chip that both includes a standard CLINT and does not add to the
  *   base set of RISC-V registers.  There are additional
- *   freertos_risc_v_port_specific_extensions.h files for RISC-V implementations
+ *   freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
  *   that do not include a standard CLINT or do add to the base set of RISC-V
  *   registers.
  *
  * CARE MUST BE TAKEN TO INCLDUE THE CORRECT
- * freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP
- * IN USE.  To include the correct freertos_risc_v_port_specific_extensions.h
+ * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP
+ * IN USE.  To include the correct freertos_risc_v_chip_specific_extensions.h
  * header file ensure the path to the correct header file is in the assembler's
  * include path.
  *
- * This freertos_risc_v_port_specific_extensions.h is for use on RISC-V chips
+ * This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
  * that include a standard CLINT and do not add to the base set of RISC-V
  * registers.
  *
  */
-#include "freertos_risc_v_port_specific_extensions.h"
+#include "freertos_risc_v_chip_specific_extensions.h"
 
-/* Check the freertos_risc_v_port_specific_extensions.h and/or command line
+/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line
 definitions. */
 #ifndef portasmHAS_CLINT
-	#error freertos_risc_v_port_specific_extensions.h must define portasmHAS_CLINT to either 1 (CLINT present) or 0 (clint not present).
+	#error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_CLINT to either 1 (CLINT present) or 0 (clint not present).
 #endif
 
 #ifndef portasmHANDLE_INTERRUPT
-	#error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts.  portasmHANDLE_INTERRUPT can be defined on the assmbler command line or in the appropriate freertos_risc_v_port_specific_extensions.h header file.
+	#error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts.  portasmHANDLE_INTERRUPT can be defined on the assmbler command line or in the appropriate freertos_risc_v_chip_specific_extensions.h header file.
 #endif
 
 /* Only the standard core registers are stored by default.  Any additional
 registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and
 portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
-specific version of freertos_risc_v_port_specific_extensions.h.  See the notes
+specific version of freertos_risc_v_chip_specific_extensions.h.  See the notes
 at the top of this file. */
 #define portCONTEXT_SIZE ( 30 * portWORD_SIZE )
 
 .global xPortStartFirstTask
-.global vFreeRTOSPortTrapHandler
+.global freertos_risc_v_trap_handler
 .global pxPortInitialiseStack
 .extern pxCurrentTCB
 .extern ulPortTrapHandler
@@ -99,7 +99,7 @@ at the top of this file. */
 
 .align 8
 .func
-vFreeRTOSPortTrapHandler:
+freertos_risc_v_trap_handler:
 	addi sp, sp, -portCONTEXT_SIZE
 	sw x1, 1 * portWORD_SIZE( sp )
 	sw x5, 2 * portWORD_SIZE( sp )
@@ -133,7 +133,7 @@ vFreeRTOSPortTrapHandler:
 	csrr t0, mstatus					/* Required for MPIE bit. */
 	sw t0, 29 * portWORD_SIZE( sp )
 
-	portasmSAVE_ADDITIONAL_REGISTERS	/* Defined in freertos_risc_v_port_specific_extensions.h to save any registers unique to the RISC-V implementation. */
+	portasmSAVE_ADDITIONAL_REGISTERS	/* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
 
 	lw  t0, pxCurrentTCB				/* Load pxCurrentTCB. */
 	sw  sp, 0( t0 )				 		/* Write sp to first TCB member. */
@@ -210,7 +210,7 @@ processed_source:
 	lw t0, 0( sp )
 	csrw mepc, t0
 
-	portasmRESTORE_ADDITIONAL_REGISTERS	/* Defined in freertos_risc_v_port_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
+	portasmRESTORE_ADDITIONAL_REGISTERS	/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
 
 	/* Load mstatus with the interrupt enable bits used by the task. */
 	lw  t0, 29 * portWORD_SIZE( sp )
@@ -258,7 +258,7 @@ xPortStartFirstTask:
 	/* If there is a clint then interrupts can branch directly to the FreeRTOS
 	trap handler.  Otherwise the interrupt controller will need to be configured
 	outside of this file. */
-	la t0, vFreeRTOSPortTrapHandler
+	la t0, freertos_risc_v_trap_handler
 	csrw mtvec, t0
 #endif /* portasmHAS_CLILNT */
 
@@ -267,7 +267,7 @@ xPortStartFirstTask:
 
 	lw  x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
 
-	portasmRESTORE_ADDITIONAL_REGISTERS	/* Defined in freertos_risc_v_port_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
+	portasmRESTORE_ADDITIONAL_REGISTERS	/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
 
     lw  t0, 29 * portWORD_SIZE( sp )    /* mstatus */
     csrrw  x0, mstatus, t0              /* Interrupts enabled from here! */
diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/readme.txt b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/readme.txt
index db628a412..b94a43687 100644
--- a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/readme.txt
+++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/readme.txt
@@ -1,27 +1,28 @@
+/*
  * The FreeRTOS kernel's RISC-V port is split between the the code that is
  * common across all currently supported RISC-V chips (implementations of the
  * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
  *
- * + The code that is common to all RISC-V chips is implemented in
- *   FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S.  There is only one
- *   portASM.S file because the same file is used no matter which RISC-V chip is
- *   in use.
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ *   is common to all currently supported RISC-V chips.  There is only one
+ *   portASM.S file because the same file is built for all RISC-V target chips.
  *
- * + The code that tailors the kernel's RISC-V port to a specific RISC-V
- *   chip is implemented in freertos_risc_v_port_specific_extensions.h.  There
- *   is one freertos_risc_v_port_specific_extensions.h that can be used with any
- *   RISC-V chip that both includes a standard CLINT and does not add to the
- *   base set of RISC-V registers.  There are additional
- *   freertos_risc_v_port_specific_extensions.h files for RISC-V implementations
- *   that do not include a standard CLINT or do add to the base set of RISC-V
- *   registers.
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
+ *   code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
+ *   chip.  There are multiple freertos_risc_v_chip_specific_extensions.h files
+ *   as there are multiple RISC-V chip implementations.
  *
- * CARE MUST BE TAKEN TO INCLDUE THE CORRECT
- * freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP
- * IN USE.  To include the correct freertos_risc_v_port_specific_extensions.h
- * header file ensure the path to the correct header file is in the assembler's
- * include path.
+ * !!!NOTE!!!
+ * CARE MUST BE TAKEN TO INCLUDE THE CORRECT
+ * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP IN USE.
+ * If the chip in use includes a core local interrupter (CLINT) and does not
+ * include any chip specific register extensions then set the GNU assembler's
+ * include path such that the header file contained in the
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32 directory is the header file that is
+ * actually inlcuded.  Otherwise set the assembler's include patch to the
+ * sub-directory off of the
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions directory
+ * that contains the freertos_risc_v_chip_specific_extensions.h specific to the
+ * target chip.
  *
- * This freertos_risc_v_port_specific_extensions.h is for use on RISC-V chips
- * that include a standard CLINT and do not add to the base set of RISC-V
- * registers.
+ */