From: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Date: Mon, 30 Jan 2017 06:36:02 +0000 (+0530)
Subject: arm64: zynqmp: zcu102: Modifying GTR lane-0 to PCIe
X-Git-Tag: v2018.01-rc1~59^2~44
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=f811eca9db05fc89fe52141b256231ff94859add;p=u-boot

arm64: zynqmp: zcu102: Modifying GTR lane-0 to PCIe

- Enabling GTR lane-0 to PCIe
- Enabling PCIe node in device tree

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index fd7d646671..df916d0f77 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -168,7 +168,7 @@
 		gtr_sel0 {
 			gpio-hog;
 			gpios = <0 0>;
-			output-high; /* PCIE = 0, DP = 1 */
+			output-low; /* PCIE = 0, DP = 1 */
 			line-name = "sel0";
 		};
 		gtr_sel1 {
@@ -551,7 +551,7 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 };
 
 &pcie {
-/*	status = "okay"; */
+	status = "okay";
 };
 
 &qspi {