From: Bin Meng Date: Fri, 11 Dec 2015 10:55:49 +0000 (-0800) Subject: x86: ivybridge: Do not require HAVE_INTEL_ME X-Git-Tag: v2016.03-rc1~311^2~10 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=fa331fad1eee0bd86470b49a905ed176aa412b9a;p=u-boot x86: ivybridge: Do not require HAVE_INTEL_ME Do not set HAVE_INTEL_ME by default as for some cases Intel ME firmware even does not reside on the same SPI flash as U-Boot. Signed-off-by: Bin Meng Acked-by: Simon Glass Tested-by: Simon Glass --- diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index 56abd8fae3..1768a26a35 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -48,7 +48,6 @@ config DCACHE_RAM_MRC_VAR_SIZE config CPU_SPECIFIC_OPTIONS def_bool y select SMM_TSEG - select HAVE_INTEL_ME select X86_RAMTEST config SMM_TSEG_SIZE diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index 6b139392b5..fa12f338de 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR select NORTHBRIDGE_INTEL_IVYBRIDGE + select HAVE_INTEL_ME select BOARD_ROMSIZE_KB_8192 config PCIE_ECAM_BASE diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig index ae96d23d03..2af3aa9e74 100644 --- a/board/google/chromebox_panther/Kconfig +++ b/board/google/chromebox_panther/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR select NORTHBRIDGE_INTEL_IVYBRIDGE + select HAVE_INTEL_ME select BOARD_ROMSIZE_KB_8192 config SYS_CAR_ADDR