From: Bin Meng <bmeng.cn@gmail.com>
Date: Tue, 30 Dec 2014 14:53:20 +0000 (+0800)
Subject: x86: Support pci bus scan in the early phase
X-Git-Tag: v2015.04-rc1~195^2~40
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=fa5530b85dd48e58700188754ee852444466bf28;p=u-boot

x86: Support pci bus scan in the early phase

On x86, some peripherals on pci buses need to be accessed in the
early phase (eg: pci uart) with a valid pci memory/io address,
thus scan the pci bus and do the corresponding resource allocation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---

diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
index 404fbb6860..1eee08b314 100644
--- a/arch/x86/cpu/pci.c
+++ b/arch/x86/cpu/pci.c
@@ -29,6 +29,7 @@ int pci_early_init_hose(struct pci_controller **hosep)
 
 	board_pci_setup_hose(hose);
 	pci_setup_type1(hose);
+	hose->last_busno = pci_hose_scan(hose);
 	gd->arch.hose = hose;
 	*hosep = hose;