From: Priyanka Jain <Priyanka.Jain@freescale.com>
Date: Thu, 7 May 2015 08:54:31 +0000 (+0530)
Subject: powerpc/t104x, t102x: Update CPC debug register value in PBI commands
X-Git-Tag: v2015.10-rc1~3^2~11
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=fa9ccff8358b010ac620b05349e300ff29f4c322;p=u-boot

powerpc/t104x, t102x: Update CPC debug register value in PBI commands

Update PBI command in pbi_cfg files to keep register bit
to default reset value while configuring CPC
as SRAM

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
---

diff --git a/board/freescale/t102xqds/t1024_pbi.cfg b/board/freescale/t102xqds/t1024_pbi.cfg
index 7b9e9b05f7..98efca25a2 100644
--- a/board/freescale/t102xqds/t1024_pbi.cfg
+++ b/board/freescale/t102xqds/t1024_pbi.cfg
@@ -6,7 +6,7 @@
 #Configure CPC1 as 256KB SRAM
 09010100 00000000
 09010104 fffc0007
-09010f00 08000000
+09010f00 081e000d
 09010000 80000000
 #Configure LAW for CPC1
 09000cd0 00000000
diff --git a/board/freescale/t102xrdb/t1024_pbi.cfg b/board/freescale/t102xrdb/t1024_pbi.cfg
index 7b9e9b05f7..98efca25a2 100644
--- a/board/freescale/t102xrdb/t1024_pbi.cfg
+++ b/board/freescale/t102xrdb/t1024_pbi.cfg
@@ -6,7 +6,7 @@
 #Configure CPC1 as 256KB SRAM
 09010100 00000000
 09010104 fffc0007
-09010f00 08000000
+09010f00 081e000d
 09010000 80000000
 #Configure LAW for CPC1
 09000cd0 00000000
diff --git a/board/freescale/t1040qds/t1040_pbi.cfg b/board/freescale/t1040qds/t1040_pbi.cfg
index 10b1a6d179..121b005baf 100644
--- a/board/freescale/t1040qds/t1040_pbi.cfg
+++ b/board/freescale/t1040qds/t1040_pbi.cfg
@@ -6,7 +6,7 @@
 #Configure CPC1 as 256KB SRAM
 09010100 00000000
 09010104 fffc0007
-09010f00 08000000
+09010f00 081e000d
 09010000 80000000
 #Configure LAW for CPC1
 09000cf0 00000000
diff --git a/board/freescale/t104xrdb/t104x_pbi.cfg b/board/freescale/t104xrdb/t104x_pbi.cfg
index b83b9b7a45..51945b4748 100644
--- a/board/freescale/t104xrdb/t104x_pbi.cfg
+++ b/board/freescale/t104xrdb/t104x_pbi.cfg
@@ -16,7 +16,7 @@
 #Configure CPC1 as 256KB SRAM
 09010100 00000000
 09010104 fffc0007
-09010f00 08000000
+09010f00 081e000d
 09010000 80000000
 #Configure LAW for CPC1
 09000cd0 00000000