From: Kever Yang Date: Thu, 30 Nov 2017 08:51:19 +0000 (+0800) Subject: rockchip: rk3036: fix pll config for correct frequency X-Git-Tag: v2018.01-rc1~25^2~8 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=faa75ad9e6de20776e4629a2eb71c372b9fcfa7d;p=u-boot rockchip: rk3036: fix pll config for correct frequency There is a fixed div-2 between PLL and clk_ddr/clk_ddrphy, so we need to double to pll output and then ddr can work in correct frequency. Signed-off-by: Kever Yang Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c index 460dd6074e..1d3fc1a622 100644 --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c @@ -34,10 +34,11 @@ struct rk3036_sdram_priv { struct rk3036_ddr_config ddr_config; }; -/* use integer mode, 396MHz dpll setting +/* + * use integer mode, dpll output 792MHz and ddr get 396MHz * refdiv, fbdiv, postdiv1, postdiv2 */ -const struct pll_div dpll_init_cfg = {1, 50, 3, 1}; +const struct pll_div dpll_init_cfg = {1, 66, 2, 1}; /* 396Mhz ddr timing */ const struct rk3036_ddr_timing ddr_timing = {0x18c,