From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Sun, 17 Jan 2016 06:03:29 +0000 (+0900)
Subject: ARM: uniphier: move UMC register macros to umc-regs.h
X-Git-Tag: v2016.03-rc1~271
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=faefef9994ed58d21f27f0b857426c0e2ad02ebe;p=u-boot

ARM: uniphier: move UMC register macros to umc-regs.h

The umc-proxstream2.c defiens the same macros as in umc-regs.h.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

diff --git a/arch/arm/mach-uniphier/dram/umc-proxstream2.c b/arch/arm/mach-uniphier/dram/umc-proxstream2.c
index 63a84e68c0..bb7acdee1e 100644
--- a/arch/arm/mach-uniphier/dram/umc-proxstream2.c
+++ b/arch/arm/mach-uniphier/dram/umc-proxstream2.c
@@ -16,54 +16,7 @@
 #include "../init.h"
 #include "../soc-info.h"
 #include "ddrmphy-regs.h"
-
-/* UM registers */
-#define UMC_MBUS0		0x00080004
-#define UMC_MBUS1		0x00081004
-#define UMC_MBUS2		0x00082004
-#define UMC_MBUS3		0x00083004
-
-/* UD registers */
-#define UMC_BITPERPIXELMODE_D0	0x010
-#define UMC_PAIR1DOFF_D0	0x054
-
-/* DC registers */
-#define UMC_INITSET		0x014
-#define UMC_INITSTAT		0x018
-#define UMC_CMDCTLA		0x000
-#define UMC_CMDCTLB		0x004
-#define UMC_SPCCTLA		0x030
-#define UMC_SPCCTLB		0x034
-#define UMC_SPCSETB		0x03c
-#define   UMC_SPCSETB_AREFMD_MASK	(0x3)	/* Auto Refresh Mode */
-#define   UMC_SPCSETB_AREFMD_ARB	(0x0)	/* control by arbitor */
-#define   UMC_SPCSETB_AREFMD_CONT	(0x1)	/* control by DRAMCONT */
-#define   UMC_SPCSETB_AREFMD_REG	(0x2)	/* control by register */
-#define UMC_ACSSETA		0x060
-#define UMC_FLOWCTLA		0x400
-#define UMC_FLOWCTLB		0x404
-#define UMC_FLOWCTLC		0x408
-#define UMC_FLOWCTLG		0x508
-#define UMC_FLOWCTLOB0		0x520
-#define UMC_FLOWCTLOB1		0x524
-#define UMC_RDATACTL_D0		0x600
-#define   UMC_RDATACTL_RADLTY_SHIFT	4
-#define   UMC_RDATACTL_RADLTY_MASK	(0xf << (UMC_RDATACTL_RADLTY_SHIFT))
-#define   UMC_RDATACTL_RAD2LTY_SHIFT	8
-#define   UMC_RDATACTL_RAD2LTY_MASK	(0xf << (UMC_RDATACTL_RAD2LTY_SHIFT))
-#define UMC_WDATACTL_D0		0x604
-#define UMC_RDATACTL_D1		0x608
-#define UMC_WDATACTL_D1		0x60c
-#define UMC_DATASET		0x610
-#define UMC_RESPCTL		0x624
-#define UMC_DCCGCTL		0x720
-#define UMC_ERRMASKA		0x958
-#define UMC_ERRMASKB		0x95c
-#define UMC_BSICMAPSET		0x988
-#define UMC_DIOCTLA		0xc00
-#define   UMC_DIOCTLA_CTL_NRST		BIT(8)	/* ctl_rst_n */
-#define   UMC_DIOCTLA_CFG_NRST		BIT(0)	/* cfg_rst_n */
-#define UMC_DFICUPDCTLA		0xc20
+#include "umc-regs.h"
 
 enum dram_freq {
 	FREQ_1866M,
diff --git a/arch/arm/mach-uniphier/dram/umc-regs.h b/arch/arm/mach-uniphier/dram/umc-regs.h
index 6159281fd3..a6957a4a51 100644
--- a/arch/arm/mach-uniphier/dram/umc-regs.h
+++ b/arch/arm/mach-uniphier/dram/umc-regs.h
@@ -69,6 +69,10 @@
 #define UMC_SPCCTLB		0x00000034
 #define UMC_SPCSETA		0x00000038
 #define UMC_SPCSETB		0x0000003C
+#define   UMC_SPCSETB_AREFMD_MASK	(0x3)	/* Auto Refresh Mode */
+#define   UMC_SPCSETB_AREFMD_ARB	(0x0)	/* control by arbitor */
+#define   UMC_SPCSETB_AREFMD_CONT	(0x1)	/* control by DRAMCONT */
+#define   UMC_SPCSETB_AREFMD_REG	(0x2)	/* control by register */
 #define UMC_SPCSETC		0x00000040
 #define UMC_SPCSETD		0x00000044
 #define UMC_SPCSTATA		0x00000050
@@ -79,17 +83,39 @@
 #define UMC_FLOWCTLB		0x00000404
 #define UMC_FLOWCTLC		0x00000408
 #define UMC_FLOWCTLG		0x00000508
+#define UMC_FLOWCTLOB0		0x00000520
+#define UMC_FLOWCTLOB1		0x00000524
 #define UMC_RDATACTL_D0		0x00000600
+#define   UMC_RDATACTL_RADLTY_SHIFT	4
+#define   UMC_RDATACTL_RADLTY_MASK	(0xf << (UMC_RDATACTL_RADLTY_SHIFT))
+#define   UMC_RDATACTL_RAD2LTY_SHIFT	8
+#define   UMC_RDATACTL_RAD2LTY_MASK	(0xf << (UMC_RDATACTL_RAD2LTY_SHIFT))
 #define UMC_WDATACTL_D0		0x00000604
 #define UMC_RDATACTL_D1		0x00000608
 #define UMC_WDATACTL_D1		0x0000060C
 #define UMC_DATASET		0x00000610
+#define UMC_RESPCTL		0x00000624
 #define UMC_DCCGCTL		0x00000720
 #define UMC_DICGCTLA		0x00000724
 #define UMC_DICGCTLB		0x00000728
+#define UMC_ERRMASKA		0x00000958
+#define UMC_ERRMASKB		0x0000095c
+#define UMC_BSICMAPSET		0x00000988
 #define UMC_DIOCTLA		0x00000C00
+#define   UMC_DIOCTLA_CTL_NRST		BIT(8)	/* ctl_rst_n */
+#define   UMC_DIOCTLA_CFG_NRST		BIT(0)	/* cfg_rst_n */
 #define UMC_DFICUPDCTLA		0x00000C20
 
+/* UM registers */
+#define UMC_MBUS0		0x00080004
+#define UMC_MBUS1		0x00081004
+#define UMC_MBUS2		0x00082004
+#define UMC_MBUS3		0x00083004
+
+/* UD registers */
+#define UMC_BITPERPIXELMODE_D0	0x010
+#define UMC_PAIR1DOFF_D0	0x054
+
 #ifndef __ASSEMBLY__
 
 #include <linux/types.h>