From: Kumar Gala Date: Tue, 22 Sep 2009 20:45:44 +0000 (-0500) Subject: ppc/85xx: Fix enabling of L2 cache X-Git-Tag: v2010.09-rc1~28^2~7^2~42^2~29 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=fd8dfa17e9a0f360414523ab441e132fa65538d7;p=u-boot ppc/85xx: Fix enabling of L2 cache We need to flash invalidate the locks in addition to the cache before we enable. Signed-off-by: Kumar Gala --- diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index a6d1e999b6..a8d83b1c8a 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -336,8 +336,8 @@ int cpu_init_r(void) u32 l2cfg0 = mfspr(SPRN_L2CFG0); /* invalidate the L2 cache */ - mtspr(SPRN_L2CSR0, L2CSR0_L2FI); - while (mfspr(SPRN_L2CSR0) & L2CSR0_L2FI) + mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); + while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) ; /* enable the cache */ diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 074b056b74..ecbd0d5857 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -102,7 +102,8 @@ __secondary_start_page: #ifdef CONFIG_BACKSIDE_L2_CACHE /* Enable/invalidate the L2 cache */ msync - lis r3,L2CSR0_L2FI@h + lis r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@h + ori r3,r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@l mtspr SPRN_L2CSR0,r3 1: mfspr r3,SPRN_L2CSR0