From: David Wu <david.wu@rock-chips.com>
Date: Wed, 20 Sep 2017 06:40:11 +0000 (+0800)
Subject: rockchip: dts: rv1108: Add SARADC node at dtsi level
X-Git-Tag: v2017.11-rc1~3^2~43
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=fdc1eccbd19e8ea45e527d2b199917c075b6a4cd;p=u-boot

rockchip: dts: rv1108: Add SARADC node at dtsi level

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

diff --git a/arch/arm/dts/rv1108.dtsi b/arch/arm/dts/rv1108.dtsi
index 3153dfe658..31b4d93b07 100644
--- a/arch/arm/dts/rv1108.dtsi
+++ b/arch/arm/dts/rv1108.dtsi
@@ -126,6 +126,17 @@
 		reg = <0x10300000 0x1000>;
 	};
 
+	saradc: saradc@1038c000 {
+		compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
+		reg = <0x1038c000 0x100>;
+		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+		#io-channel-cells = <1>;
+		clock-frequency = <1000000>;
+		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+		clock-names = "saradc", "apb_pclk";
+		status = "disabled";
+	};
+
 	pmugrf: syscon@20060000 {
 		compatible = "rockchip,rv1108-pmugrf", "syscon";
 		reg = <0x20060000 0x1000>;