From: Marek Vasut <marek.vasut@gmail.com>
Date: Sat, 13 May 2017 13:57:48 +0000 (+0200)
Subject: ARM: rmobile: salvator-x: Add DVFS and PMIC support
X-Git-Tag: v2017.07-rc1~191^2~6
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=fe2e8ff955ad18a7f7f26d3d56ebaa96167139b6;p=u-boot

ARM: rmobile: salvator-x: Add DVFS and PMIC support

Add support for rebooting the board using the ROHM BD9571MWV I2C PMIC,
but keep the CPU reboot option as a fallback.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---

diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c
index 38ff99a17c..acc541df0c 100644
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -50,6 +50,7 @@ void s_init(void)
 #define TMU1_MSTP124		BIT(24)	/* non-secure */
 #define SCIF2_MSTP310		BIT(10)	/* SCIF2 */
 #define ETHERAVB_MSTP812	BIT(12)
+#define DVFS_MSTP926		BIT(26)
 #define SD0_MSTP314		BIT(14)
 #define SD1_MSTP313		BIT(13)
 #define SD2_MSTP312		BIT(12)	/* either MMC0 */
@@ -78,6 +79,10 @@ int board_early_init_f(void)
 	writel(0, SD2CKCR);
 	writel(0, SD3CKCR);
 
+#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
+	/* DVFS for reset */
+	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
+#endif
 	return 0;
 }
 
@@ -235,8 +240,12 @@ const struct rmobile_sysinfo sysinfo = {
 
 void reset_cpu(ulong addr)
 {
+#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
+	i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
+#else
 	/* only CA57 ? */
 	writel(RST_CODE, RST_CA57RESCNT);
+#endif
 }
 
 static const struct sh_serial_platdata serial_platdata = {
diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h
index b5a98d6db2..0e5c130b13 100644
--- a/include/configs/salvator-x.h
+++ b/include/configs/salvator-x.h
@@ -50,6 +50,18 @@
 #define GICD_BASE	0xF1010000
 #define GICC_BASE	0xF1020000
 
+/* i2c */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SH
+#define CONFIG_SYS_I2C_SLAVE		0x60
+#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS	1
+#define CONFIG_SYS_I2C_SH_SPEED0	400000
+#define CONFIG_SH_I2C_DATA_HIGH		4
+#define CONFIG_SH_I2C_DATA_LOW		5
+#define CONFIG_SH_I2C_CLOCK		10000000
+
+#define CONFIG_SYS_I2C_POWERIC_ADDR	0x30
+
 /* SDHI */
 #define CONFIG_SH_SDHI_FREQ		200000000