From: richardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Date: Tue, 16 Apr 2013 14:17:35 +0000 (+0000)
Subject: Replace the read back of the software interrupt register with barrier instructions... 
X-Git-Tag: V7.4.1~17
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=fedf637160e067c1e6fe79c20e81aaa45d8ad3c7;p=freertos

Replace the read back of the software interrupt register with barrier instructions (CCS/RM48/TMS570).

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1858 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
---

diff --git a/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portmacro.h b/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portmacro.h
index 9d3aeceb5..3c665fc90 100644
--- a/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portmacro.h
+++ b/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portmacro.h
@@ -56,19 +56,19 @@
     ***************************************************************************
 
 
-    http://www.FreeRTOS.org - Documentation, books, training, latest versions, 
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
     license and Real Time Engineers Ltd. contact details.
 
     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
     including FreeRTOS+Trace - an indispensable productivity tool, and our new
     fully thread aware and reentrant UDP/IP stack.
 
-    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High 
-    Integrity Systems, who sell the code with commercial support, 
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems, who sell the code with commercial support,
     indemnification and middleware, under the OpenRTOS brand.
-    
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety 
-    engineered and independently SIL3 certified version for use in safety and 
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
     mission critical applications that require provable dependability.
 */
 
@@ -105,7 +105,7 @@
 
 /* Architecture specifics. */
 #define portSTACK_GROWTH    (-1)
-#define portTICK_RATE_MS    ((portTickType) 1000 / configTICK_RATE_HZ)		
+#define portTICK_RATE_MS    ((portTickType) 1000 / configTICK_RATE_HZ)
 #define portBYTE_ALIGNMENT  8
 
 /* Critical section handling. */
@@ -122,7 +122,7 @@ extern void vPortYield( void );
 #define portYIELD()             	vPortYield()
 #define portSYS_SSIR1_REG			( * ( ( volatile unsigned long * ) 0xFFFFFFB0 ) )
 #define portSYS_SSIR1_SSKEY			( 0x7500UL )
-#define portYIELD_WITHIN_API()		{ portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY;  ( void ) portSYS_SSIR1_REG; }
+#define portYIELD_WITHIN_API()		{ portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY;  asm( " DSB " ); asm( " ISB " ); }
 #define portYIELD_FROM_ISR( x )		if( x != pdFALSE ){ portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY;  ( void ) portSYS_SSIR1_REG; }
 
 /* Architecture specific optimisations. */