From: Chen-Yu Tsai Date: Mon, 7 May 2018 07:33:24 +0000 (+0530) Subject: sunxi: clock: Fix OHCI clock gating for H3/H5 X-Git-Tag: v2018.07-rc1~8^2~28 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=fef73766d9ad4ca76b47faf6436f096ec40b3e7c;p=u-boot sunxi: clock: Fix OHCI clock gating for H3/H5 Clock gating bits on H43/H5 were wrong, fix them. Signed-off-by: Chen-Yu Tsai Reviewed-by: Jagan Teki Acked-by: Jun Nie --- diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 87d82f205c..8acf79fbba 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -350,13 +350,10 @@ struct sunxi_ccm_reg { #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) #define CCM_USB_CTRL_PHY3_CLK (0x1 << 11) #ifdef CONFIG_MACH_SUNXI_H3_H5 -/* - * These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call - * them 0 - 2 like they were called on older SoCs. - */ -#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 17) -#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 18) -#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 19) +#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) +#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) +#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 18) +#define CCM_USB_CTRL_OHCI3_CLK (0x1 << 19) #else #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)