From: Romain Perier Date: Fri, 2 Jun 2017 09:19:43 +0000 (+0200) Subject: rockchip: rk3288: grf: Fix shift for RK3288_TXCLK_DLY_ENA_GMAC_ENABLE X-Git-Tag: v2017.07-rc2~80^2~10 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=fefe9d06bd0917739822a4be4c702f1d5d0e0899;p=u-boot rockchip: rk3288: grf: Fix shift for RK3288_TXCLK_DLY_ENA_GMAC_ENABLE RK3288_TXCLK_DLY_ENA_GMAC_ENABLE, in GRF_SOC_CON3, is supposed to be bit 0xe and not 0xf. Otherwise, it is RGMII RX clock delayline enable and introduces random delays and data lose. This commit fixes the issue by replacing RK3288_TXCLK_DLY_ENA_GMAC_ENABLE with the right shift. Signed-off-by: Romain Perier Reviewed-by: Simon Glass --- diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h index 7d56b8ced0..fbc4a0d80f 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h @@ -813,7 +813,7 @@ enum { (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT), RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0, RK3288_TXCLK_DLY_ENA_GMAC_ENABLE = - (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT), + (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT), RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, RK3288_CLK_RX_DL_CFG_GMAC_MASK =