From: Akshay Saraswat Date: Thu, 21 Mar 2013 20:33:04 +0000 (+0000) Subject: Exynos: uart: s5p: enabling the uart tx/rx fifo X-Git-Tag: v2013.07-rc2~60^2~10^2~16 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=ffbff1dd6e6a25cc7db60576ad64e7bd570fa643;p=u-boot Exynos: uart: s5p: enabling the uart tx/rx fifo This patch enables the uart tx/rx fifo. Now that fifo is enabled, the uart read/write functions are modfied to check the UFSTAT register for fifo status instead of UTRSTAT (as required with fifo's enabled). Tested by booting linux kernel. Before enabling tx/rx fifo "Uncompressing linux" message is garbled and after enabling it is proper. Signed-off-by: Alim Akhtar Signed-off-by: Akshay Saraswat Signed-off-by: Minkyu Kang --- diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c index 3c41242a8e..e65125ccd7 100644 --- a/drivers/serial/serial_s5p.c +++ b/drivers/serial/serial_s5p.c @@ -30,6 +30,10 @@ DECLARE_GLOBAL_DATA_PTR; +#define RX_FIFO_COUNT_MASK 0xff +#define RX_FIFO_FULL_MASK (1 << 8) +#define TX_FIFO_FULL_MASK (1 << 24) + static inline struct s5p_uart *s5p_get_base_uart(int dev_index) { u32 offset = dev_index * sizeof(struct s5p_uart); @@ -87,8 +91,8 @@ int serial_init_dev(const int dev_index) { struct s5p_uart *const uart = s5p_get_base_uart(dev_index); - /* reset and enable FIFOs, set triggers to the maximum */ - writel(0, &uart->ufcon); + /* enable FIFOs */ + writel(0x1, &uart->ufcon); writel(0, &uart->umcon); /* 8N1 */ writel(0x3, &uart->ulcon); @@ -130,7 +134,8 @@ int serial_getc_dev(const int dev_index) struct s5p_uart *const uart = s5p_get_base_uart(dev_index); /* wait for character to arrive */ - while (!(readl(&uart->utrstat) & 0x1)) { + while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | + RX_FIFO_FULL_MASK))) { if (serial_err_check(dev_index, 0)) return 0; } @@ -146,7 +151,7 @@ void serial_putc_dev(const char c, const int dev_index) struct s5p_uart *const uart = s5p_get_base_uart(dev_index); /* wait for room in the tx FIFO */ - while (!(readl(&uart->utrstat) & 0x2)) { + while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { if (serial_err_check(dev_index, 1)) return; }