From: Philipp Tomsich Date: Fri, 28 Apr 2017 16:33:57 +0000 (+0200) Subject: rockchip: clk: rk3399: allow requests for HDMI clocks X-Git-Tag: v2017.07-rc1~356^2~19 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=ffc1fac549d72ce85205dcdde9af9dfe0f04fd76;p=u-boot rockchip: clk: rk3399: allow requests for HDMI clocks This allows requests (via the DTS) for PCLK_HDMI_CTRL/PCLK_VIO_GRF, which are clock gates in the HDMI output path for the RK3399. As these are enabled by default (i.e. after reset), we don't implement any logic to actively open/close these clock gates and simply assume that their reset-default has not been changed. Signed-off-by: Philipp Tomsich Reviewed-by: Simon Glass --- diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 10db46e400..026ed4dde7 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -882,6 +882,9 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case SCLK_UART0: case SCLK_UART2: return 24000000; + break; + case PCLK_HDMI_CTRL: + break; case DCLK_VOP0: case DCLK_VOP1: break; @@ -922,6 +925,10 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) case SCLK_SPI0...SCLK_SPI5: ret = rk3399_spi_set_clk(priv->cru, clk->id, rate); break; + case PCLK_HDMI_CTRL: + case PCLK_VIO_GRF: + /* the PCLK gates for video are enabled by default */ + break; case DCLK_VOP0: case DCLK_VOP1: ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);