From: Olli Savia Date: Sat, 14 Apr 2018 15:45:15 +0000 (+0300) Subject: Changed register addresses relative to the base address X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=refs%2Fpull%2F625%2Fhead;p=cc65 Changed register addresses relative to the base address --- diff --git a/asminc/vic20.inc b/asminc/vic20.inc index 9c8ca8a35..6ac7ef35c 100644 --- a/asminc/vic20.inc +++ b/asminc/vic20.inc @@ -67,42 +67,42 @@ VIC_COLOR := $900F ; Border and background color ; I/O: 6522 VIA1 VIA1 := $9110 ; VIA1 base address -VIA1_JOY := $9111 ; *** Deprecated *** -VIA1_PB := $9110 ; Port register B -VIA1_PA1 := $9111 ; Port register A -VIA1_DDRB := $9112 ; Data direction register B -VIA1_DDRA := $9113 ; Data direction register A -VIA1_T1CL := $9114 ; Timer 1, low byte -VIA1_T1CH := $9115 ; Timer 1, high byte -VIA1_T1LL := $9116 ; Timer 1 latch, low byte -VIA1_T1LH := $9117 ; Timer 1 latch, high byte -VIA1_T2CL := $9118 ; Timer 2, low byte -VIA1_T2CH := $9119 ; Timer 2, high byte -VIA1_SR := $911A ; Shift register -VIA1_CR := $911B ; Auxiliary control register -VIA1_PCR := $911C ; Peripheral control register -VIA1_IFR := $911D ; Interrupt flag register -VIA1_IER := $911E ; Interrupt enable register -VIA1_PA2 := $911F ; Port register A w/o handshake +VIA1_JOY := VIA1+$0 ; *** Deprecated *** +VIA1_PB := VIA1+$0 ; Port register B +VIA1_PA1 := VIA1+$1 ; Port register A +VIA1_DDRB := VIA1+$2 ; Data direction register B +VIA1_DDRA := VIA1+$3 ; Data direction register A +VIA1_T1CL := VIA1+$4 ; Timer 1, low byte +VIA1_T1CH := VIA1+$5 ; Timer 1, high byte +VIA1_T1LL := VIA1+$6 ; Timer 1 latch, low byte +VIA1_T1LH := VIA1+$7 ; Timer 1 latch, high byte +VIA1_T2CL := VIA1+$8 ; Timer 2, low byte +VIA1_T2CH := VIA1+$9 ; Timer 2, high byte +VIA1_SR := VIA1+$A ; Shift register +VIA1_CR := VIA1+$B ; Auxiliary control register +VIA1_PCR := VIA1+$C ; Peripheral control register +VIA1_IFR := VIA1+$D ; Interrupt flag register +VIA1_IER := VIA1+$E ; Interrupt enable register +VIA1_PA2 := VIA1+$F ; Port register A w/o handshake ; --------------------------------------------------------------------------- ; I/O: 6522 VIA2 VIA2 := $9120 ; VIA2 base address -VIA2_JOY := $9120 ; *** Deprecated *** -VIA2_PB := $9120 ; Port register B -VIA2_PA1 := $9121 ; Port register A -VIA2_DDRB := $9122 ; Data direction register B -VIA2_DDRA := $9123 ; Data direction register A -VIA2_T1CL := $9124 ; Timer 1, low byte -VIA2_T1CH := $9125 ; Timer 1, high byte -VIA2_T1LL := $9126 ; Timer 1 latch, low byte -VIA2_T1LH := $9127 ; Timer 1 latch, high byte -VIA2_T2CL := $9128 ; Timer 2, low byte -VIA2_T2CH := $9129 ; Timer 2, high byte -VIA2_SR := $912A ; Shift register -VIA2_CR := $912B ; Auxiliary control register -VIA2_PCR := $912C ; Peripheral control register -VIA2_IFR := $912D ; Interrupt flag register -VIA2_IER := $912E ; Interrupt enable register -VIA2_PA2 := $912F ; Port register A w/o handshake +VIA2_JOY := VIA2+$0 ; *** Deprecated *** +VIA2_PB := VIA2+$0 ; Port register B +VIA2_PA1 := VIA2+$1 ; Port register A +VIA2_DDRB := VIA2+$2 ; Data direction register B +VIA2_DDRA := VIA2+$3 ; Data direction register A +VIA2_T1CL := VIA2+$4 ; Timer 1, low byte +VIA2_T1CH := VIA2+$5 ; Timer 1, high byte +VIA2_T1LL := VIA2+$6 ; Timer 1 latch, low byte +VIA2_T1LH := VIA2+$7 ; Timer 1 latch, high byte +VIA2_T2CL := VIA2+$8 ; Timer 2, low byte +VIA2_T2CH := VIA2+$9 ; Timer 2, high byte +VIA2_SR := VIA2+$A ; Shift register +VIA2_CR := VIA2+$B ; Auxiliary control register +VIA2_PCR := VIA2+$C ; Peripheral control register +VIA2_IFR := VIA2+$D ; Interrupt flag register +VIA2_IER := VIA2+$E ; Interrupt enable register +VIA2_PA2 := VIA2+$F ; Port register A w/o handshake