]> git.sur5r.net Git - u-boot/history - board/xaeniax/lowlevel_init.S
Modified the DDR SDRAM clock control register to delay MCK/MCK_B 3/4 clock
[u-boot] / board / xaeniax / lowlevel_init.S
2005-04-02 wdenkPrepare for SoC rework of ARM code: