- sw_bkpts fails if the target is not halted. The side effect is
that sw_bkpts also fails if the target is an unknown state(i.e.
not examined yet).
- feroceon embedded ICE registers are now set up after TRST
has been deasserted(not tested, but it was broken as is
anyway).
added target->type->examine(). Eventually this will allow for bringing up telnet/gdb *before* jtag chain has been validated + it might fix some reset halt problems seen as examine() needs to run after TRST has been asserted.
- single core context used, removed debug context as thought unnecessary.
- DCRDR now used to access special core registers - info is currently omitted from the cortex_m3 TRM ARM have told me this is the preferred access method and the docs will be updated soon.
- now checks for User Thread Mode and Thread mode when halted.
- removed repeated function declarations from command.c
- cortex_m3_prepare_reset_halt removed, updated cortex_m3_assert_reset to suit
- added "init" command. "init" and "reset" at end of startup script is equivalent
to daemon_startup(still supported).
- print warning if srst and trst change state at the same time when srst_and_trst
is seperate
- reset now performs a trst, examines and validates the jtag chain before targets
assert reset
- if startup fails to examine and validate the jtag chain, try a reset before
trying again
- only if "reset halt" or "reset init" are issued will the reset vector be set up
- If communication fails during assert between assert/deassert and during
assert, warnings are printed. The warning suggests using srst_only if the
clock locks up as that would allow the reset vector to be set up before
asserting reset.
- the reset mode parameter is now DEPRECATED. It is implemented
as an optional parameter with default reset_init. This is to streamline
things w.r.t. the target library.
- reverted some of the changes that possibly broke arm926ejs. Waiting
for a bit more info before I can tell with confidence whether or not
this would have any effect.
- worked on error propagation and output for flash
- Work on fixing erase check. Many implementations are plain broken.
Wrote a default flash erase check fn which uses CFI's target algorithm
w/fallback to memory reads.
- "flash info" no longer prints erase status as it is stale.
- "flash erase_check" now prints erase status. erase check can take a
*long* time. Work in progress
- arm7/9 with seperate srst & trst now supports reset init/halt
after a power outage. arm7/9 no longer makes any assumptions
about state of target when reset is asserted.
- fixes for srst & trst capable arm7/9 with reset init/halt
- prepare_reset_halt retired. This code needs to be inside
assert_reset anyway
- haven't been able to get stm32 write algorithm to work. Fallback
flash write does work. Haven't found a version of openocd trunk
where this works.
- added target_free_all_working_areas_restore() which can
let be of restoring backups. This is needed when asserting
reset as the target must be assumed to be an unknown state.
Added some comments to working areas API
- str9 reset script fixes
- some guidelines
- fixed dangling callbacks upon reset timeout
ntfreak [Fri, 21 Mar 2008 12:53:29 +0000 (12:53 +0000)]
- armv7m control register now set as dirty when switching context
- armv7m added core_mode to cortex_m3_debug_entry DEBUG msg
- cortex_m3 changed WARNINGS to DEBUG msg in cortex_m3_resume
drath [Mon, 17 Mar 2008 21:39:18 +0000 (21:39 +0000)]
- fix warnings during configure cause by ecosboard. default to no, if host cpu isn't arm.
- fix generic bitbang code to allow scans to end in Shift-[ID]R
- several CFI fixes (thanks to Michael Schwingen):
- buffer overflow when converting target code in cfi_intel_write_block -
cfi_fix_code_endian needs the number of words, not bytes, as size
argument.
- Spansion flash write was completely broken on big-endian targets - I
borrowed mechanisms from the intel driver, and moved some common code
into the cfi_command_val helper function. There is still more common code
that might be cleaned up.
- the buffer size check in cfi_write was broken for spansion flashes, where
cfi_write_words is not implemented. cfi_write_words is no only called if
the flash does have a buffer size >1.
- "flash info" printed CFI status information for non-CFI flashes, which is
confusing. It now only prints those when a real CFI flash is detected.
oharboe [Thu, 13 Mar 2008 10:14:41 +0000 (10:14 +0000)]
- adds two speeds to jtag_speed. reset and post reset speed. Default
is post reset = reset speed.
- removed infinite loop's and exit()'s upon poor arm7/9 communication
- cleaned up error messages a bit. Push ERROR() up into fn's that
fail and can say something meaningful about what failed.
oharboe [Tue, 11 Mar 2008 21:32:03 +0000 (21:32 +0000)]
reduce compare noise. If someone should be crazy enough to try to run OpenOCD under eCos, then they'v got some hooks to point them in the general direction.
oharboe [Tue, 11 Mar 2008 21:16:57 +0000 (21:16 +0000)]
- retired unused jtag events. The code was incorrect
- hopefully clarified the difference between TRST and TMS reset.
- added DEBUG() statements w.r.t. state changes
- TRST released and moving out of TAP_TLR are completely
different events. Only TRST released has a DEBUG() statement
ntfreak [Tue, 11 Mar 2008 18:39:43 +0000 (18:39 +0000)]
- 16 and 32 bit unaligned accesses supported
- uses packed transfers for 8/16bit read/writes greater than 4bytes
- 8/16bit transfers now use address auto increment
oharboe [Tue, 11 Mar 2008 09:06:00 +0000 (09:06 +0000)]
- fixed jtag_add_reset(). It no longer causes jtag_execute_queue() to
fail for two of it's return codes. A little bit weird, but compatible with
existing codebase.
- tightend up error handling. Since the jtag_xxx() is a queue that is either
executed as things are added(hw queue) or a software queue, then
errors can only be caught during jtag_execute_queue(). No error
code is therefore returned from the queuing fn's.
oharboe [Mon, 10 Mar 2008 14:14:15 +0000 (14:14 +0000)]
- fixed a problem with big endian XScale and GDB register packets.
- hmm..... did I screw up? Was XScale and not gdb_server busted here?
My thinking was that OpenOCD has a canonical internal representation
of registers that match GDB's expectations
oharboe [Mon, 10 Mar 2008 14:07:28 +0000 (14:07 +0000)]
- the jtag chain is examined and validated after GDB & telnet servers
are up and running. The examination and validation is actually
"optional" from the point of view of GDB + telnet servers.
Multiple targets should work fine with this.
- jtag_speed is dropped(divisor is increased), if jtag examination and
validation fails.
- the chain is validated 10x to catch the worst jtag_speed offences
- added LOG_SILENT that can be used to shut up log. Feeble
ersatz for try+catch.
- GDB register packets are now always replied in order to make sure
that GDB connect works. If the target is not halted, then these
packets contain dummy values.
projects / openocd / log