Andrey Skvortsov [Wed, 25 May 2016 10:11:18 +0000 (13:11 +0300)]
flash: nor: mdr: fix verification problem with 1986VE1T or 1986VE3T
1986VE1T and 1986VE3T have issue with flash acceleration engine described
in their errata (issue 0007).
After programming flash acceleration engine's buffer contains old data,
and therefore first read data are wrong. Because of this verification after
programming fails always. Recommended workaround for the issue is to flush
flash accelerator's buffer. To do so it's necessary to read at least 64
bytes of flash through accelerator.
Reading bytes through JTAG using default_flash_read doesn't help.
It seems that reading should be done by uC itself.
Steven Stallion [Mon, 11 Jul 2016 19:18:54 +0000 (14:18 -0500)]
server: support binding to arbitrary interfaces
Some installations of OpenOCD are used in restricted environments that
do not permit binding to public interfaces.
This patch does not affect the default behavior to listen on all
interfaces, however it does give the option to restrict services by way
of the bindto command.
Change-Id: Id51bd64b376a8c62dd47b08b4d834872925e6af2 Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/3534 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Today the reset option for connect_assert_srst is not done for SWD.
This patch adds this to SWD and make it possible to connect to targets which might disable JTAG interface when running.
Change-Id: Ib89f7cf59b628e8f0b5fca9dd9e362e383c4b99f Signed-off-by: Fredrik Hederstierna <fredrik@hederstierna.com>
Reviewed-on: http://openocd.zylin.com/3018 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Esben Haabendal [Fri, 27 Nov 2015 08:13:36 +0000 (09:13 +0100)]
cfi: Add support for strangely endianness broken SoC implementations
This adds the 'data_swap' parameter to the CFI driver, which enables
swapping of data bytes when writing/programming words to the flash.
Note, that this specifically means that bytes are not swapped when
writing command words to the flash chip. Unless you are using the SAP
in an LS102x chip to program an attached 16-bit NOR flash, you hopefully
do not need this!
Esben Haabendal [Tue, 10 Nov 2015 10:44:29 +0000 (11:44 +0100)]
Support for Freescale LS102x SAP
The SAP in LS102x SoC's from Freescale is able to read and write to all
physical memory locations, independently of CPU cores and DAP.
This implementation is 100% based on reverse-engineering of JTAG
communication with an LS1021A SAP using a JTAG debugger with SAP support.
And as such, this code is for now "works-for-me", pending verification
by other OpenOCD users, or even better, actual information from Freescale
on the SAP interface.
Tim Newsome [Thu, 19 May 2016 02:39:52 +0000 (19:39 -0700)]
Fix comment that limits num_bits to 32.
Andreas Fritiofson says "If any adapter driver does not work with
arbitrary lengths of individual fields, it's a bug."
https://sourceforge.net/p/openocd/mailman/message/35091945/
Note also that lengths of at least 96 bits are already in use, eg. in
mips_ejtag_add_scan_96().
Change-Id: I62a150adc75c0ef78827683ca8d0a8e90310a982 Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/3491 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Paul Fertser [Sat, 7 May 2016 16:35:22 +0000 (19:35 +0300)]
configure.ac: support MSYS with newer config.guess
Upstream commit
http://git.savannah.gnu.org/gitweb/?p=config.git;a=commitdiff;h=f4ebd3ed097771a729b68e688236aea665e7c1f3
makes both i386 and amd64 MSYS (and MSYS2) systems be detected as
*-pc-msys .
With this patch OpenOCD builds without any additional tweaks on MSYS2
with the latest config.guess.
Change-Id: I1ae4154f76125a84078926b425fa989904639ce0 Reported-by: "Stevens, Kelly E. M." <Kelly.Stevens@gtri.gatech.edu> Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3468 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Andreas Färber [Sun, 12 Jul 2015 13:45:20 +0000 (15:45 +0200)]
lpcspifi: Fix SWD support for LPC43xx
When using SWD rather than JTAG transport, the lpcspifi driver complains:
Error: Device ID 0x0 is not known as SPIFI capable
Error: auto_probe failed
This is because target's JTAG tap->idcode is zero for SWD.
Drop this check completely and hardcode the addresses for now. Neither
the JTAG TAPID nor the SWD IDCODE are unique enough to detect the exact
chip model and thereby its memory map.
Marc Schink [Sun, 17 Apr 2016 12:53:25 +0000 (14:53 +0200)]
board/efm32: Disable SRST
The current configuration leads to the following error when trying to
program the target:
SWD IDCODE 0x2ba01477
timed out while waiting for target halted
TARGET: efm32.cpu - Not halted
in procedure 'program'
in procedure 'reset' called at file "embedded:startup.tcl", line 478
in procedure 'ocd_bouncer'
Use the default reset handling of the target (SYSRESETREQ) to reset the
system rather than SRST to fix the problem.
Tested on EFM32GG, EFM32TG and EZR32WG STK.
Change-Id: I788c41baf08b20814cbe0934b563424c4bc144b8 Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3420 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Consistently write it the official way, so that it stops propagating.
Originally spotted in the documentation, it mainly affects code comments
but also Atmel SAM3/SAM4/SAMV, NiietCM4 and SiM3x flash driver output.
Samuel Martin [Wed, 18 May 2016 23:15:52 +0000 (01:15 +0200)]
tcl: add STM32F429I-DISC1 board config
Both the STM32F429I-DISC{O,1} boards are equipped with the same MCU, but
differ by the debugging chip:
- the STM32F429I-DISCO uses the ST-LINK/V2 chip;
- the STM32F429I-DISC1 uses the ST-LINK/V2-B chip (which matches the USB
VID/PID set in stlink-v2-1.cfg).
Change-Id: I07d637f72d26cf5d714472638da974eb6ca02325 Signed-off-by: Samuel Martin <s.martin49@gmail.com>
Reviewed-on: http://openocd.zylin.com/3492 Reviewed-by: Andreas Färber <afaerber@suse.de> Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Memory accesses are not made through the APB-AP, they are made through
the CPU (which happens to be controlled over the APB-AP). Rename all
irrelevant uses of the APB-AP term. And fix the long standing typo in
the function names...
Change-Id: Ide466fb2728930968bdba698f0dd9012cc9dbdf9 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3216 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Andreas Färber [Sat, 14 May 2016 13:02:44 +0000 (15:02 +0200)]
arm_adi_v5: Add part numbers for Infineon XMC4000 family
This was found on multiple XMC4500:
Valid ROM table present
Component base address 0xe00ff000
Peripheral ID 0x00001c11db
Designer is 0x0c1, Infineon (Siemens)
Part is 0x1db, Unrecognized
Component class is 0x1, ROM table
MEMTYPE system memory present on bus
On multiple XMC4700 and an XMC4800 this was found instead:
Valid ROM table present
Component base address 0xe00ff000
Peripheral ID 0x00001c11df
Designer is 0x0c1, Infineon (Siemens)
Part is 0x1df, Unrecognized
Component class is 0x1, ROM table
MEMTYPE system memory present on bus
Name them "XMC4500 ROM" and "XMC4700/4800 ROM" respectively.
Andreas Färber [Sat, 14 May 2016 12:55:38 +0000 (14:55 +0200)]
arm_adi_v5: Add part number for Infineon XMC1000 family
Not documented in the Reference Manuals but found on multiple XMC1100/1202:
Valid ROM table present
Component base address 0xf0000000
Peripheral ID 0x00001c11ed
Designer is 0x0c1, Infineon (Siemens)
Part is 0x1ed, Unrecognized
Component class is 0x1, ROM table
MEMTYPE system memory present on bus
Name it "XMC1000 ROM", since it didn't differ between XMC1100 and XMC1200.
Alexander Kurz [Sun, 14 Feb 2016 09:04:51 +0000 (10:04 +0100)]
jtag ulink: dont compile function when not required
ulink_calculate_frequency() is used exclusively when
_DEBUG_JTAG_IO_ is set, no need to compile this
function if it is not used.
Declaring it static in the same commit.
Change-Id: I243ffdf69a1dc3bee6d16e4bb8d78396b6ea5144 Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3241 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Alexander Kurz [Tue, 1 Mar 2016 08:32:49 +0000 (09:32 +0100)]
udev: add rule for original Keil ULink (version 1)
The original ULINK adapter has been introduced by Keil in 2002 and got
replaced in 2008 by the incompatible ULINK2. It is not listed on their
website any more. For information about it, browse archive.org
for http://www.keil.com/ulink1/ or http://www.keil.com/ulink/
Change-Id: Ie52d381580acab53ddb40499594dbdc2d27ef1b6 Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3371 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Andreas Färber [Sat, 14 May 2016 18:57:55 +0000 (20:57 +0200)]
doc: Fix mismerges of fm4, kinetis and kinetis_ke flash drivers
Commit dfc6658cf98d494e066426945879b9f60bbf9678 ("Kinetis: flash
driver described in openocd.texi") inserted a kinetis section between
fm3 and lpc2000. Then commit 43ff5acd45017fd9828cc56f54b929e600956c3b
("flash: New Spansion FM4 flash driver") was merged, inserting the fm4
section between kinetis and lpc2000, instead of after fm3. Finally
kinetis_ke was added between kinetis and fm4 in commit 5396ec5dcc64354c8101f8d3f16d498ca3b10326 ("flash: Added support for
Freescale Kinetis KE family.").
Restore the alphabetical order by moving the fm4 section to before
kinetis.
Change-Id: I77e47c3cd5b2cd8570b62ff2f7be8526aaf57ad0 Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3484 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Marc Schink <openocd-dev@marcschink.de>
Andreas Färber [Sat, 14 May 2016 11:59:40 +0000 (13:59 +0200)]
arm_adi_v5: Reorder Atmel part number entry
Instead of placing Atmel last, after ANY_ID, place it after ARM (it's
arm_adi_v5 despite 0x4BB) and sort it with the other vendors, i.e.
before ADI and Qualcomm. Adapt column alignment.
Drop the redundant "Atmel" comment to clarify that Analog is not Atmel.
Jiri Kastner [Thu, 5 May 2016 09:35:10 +0000 (11:35 +0200)]
arm_adi_v5: added partnumber for APQ8016
On APQ8016 was found a CoreSight component designed by
Qualcomm, according to db410c HRM [1] it has a partnumber
following this schema:
[11:8] is 0x4 meaning Qualcomm designed Coresight component in QDSS. Reads as 0x4.
[7:6] is Subsystem/core family ID (e.g. denote QDSS family or generation).
[5:4] is Subsystem/core configuration options (e.g. denote cache options, etc.).
[3:2] is Subsystem/core fuse options.
[1:0] is Subsystem/core future use field
Reads as 0x440.
arm7_9_common.c: In function ‘arm7_9_unset_breakpoint’:
arm7_9_common.c:353:4: error: this ‘if’ clause does not guard... [-Werror=misleading-indentation]
if (current_instr == arm7_9->thumb_bkpt)
^~
arm7_9_common.c:356:5: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘if’
if (retval != ERROR_OK)
^~
The logic won't change once the braces have been added, as the new 'retval'
check only makes sense within the if().
Alexander Kurz [Sat, 13 Feb 2016 12:48:02 +0000 (13:48 +0100)]
Helper ioutil: cleanup: removing dead code
The ioutil helper functions copyfile and copydir were last and only used
in ecosboard.c which has been removed with commit 39650e22.
Removing the dead code.
Change-Id: I36c7c4c5009d755b4513a14a9f9e214d1ee500e8 Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3240 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Uwe Bonnes [Wed, 2 Mar 2016 11:54:07 +0000 (12:54 +0100)]
stlink: Decode more errors.
For STLINK_SWD_AP_FAULT git://git.ac6.fr/openocd commit 657e3e885b9ee10
returns ERROR_OK with the comment:
Change in error status when reading outside RAM.
This fix allows CDT plugin to visualize memory.
Lieven Hollevoet [Fri, 25 Mar 2016 14:05:35 +0000 (15:05 +0100)]
Support for debug interface lock of EFM32 controllers
The capability to lock the debug interface on EFM32
controllers was lacking in OpenOCD.
After receiving some pointers by zapb_ and PaulFertser
on IRC (thanks guys!) I have added this capability.
This works by writing the required bits in the debug
lock word to '0'.
Note: there is currently no way to re-enable the debug
interface from OpenOCD as doing this requires specific
pin wiggling that is currently not implemented yet.
However: having the capability to lock the debug interface
is useful when building a volume programming jig.
You can flash the program code, verify and then
lock the debug interface so that the device cannot
be read when it is deployed in the field.
Christopher Head [Thu, 21 Apr 2016 00:31:12 +0000 (17:31 -0700)]
Add Altera USB Blaster udev rule.
This udev rule makes the Altera USB Blaster clone I have on my desk
accessible to the plugdev group.
Change-Id: Ic5e8052c66a270b6a6f89e29de49d9785f18fc1e Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/3423 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
ftdi: make ftdi_location command depend on libusb1 version
The function libusb_get_port_numbers(), required for the command
ftdi_location, is only available in recent version of libusb1.
Compilation will break if the function is not available. This patch
enables the command only if libusb1 contains the necessary function.
Salvador Arroyo [Sun, 24 Aug 2014 18:56:05 +0000 (20:56 +0200)]
MIPS32 Fix typos
I suppose 0xff300008 is the correct value for EJTAG_V20_DBS.
20 miliseconds is too much for scan delay, 2ms is enough in mips_m4k scan_delay handler.
mips32 scan_delay has the correct value.
Change-Id: Ie9dc650065a58e845687058a4c930f85909beec9 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/2271 Tested-by: jenkins Reviewed-by: Kent Brinkley <jkbrinkley.imgtec@gmail.com> Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Salvador Arroyo [Sun, 24 Aug 2014 17:34:08 +0000 (19:34 +0200)]
Fix for BMIPS
BMIPS always needs 2 additional instructions to reach the core.
Seems there is a 2 instructions fifo between the tap and the core, or it behaves in this way.
No idea of the purpose of this fifo, I can only guess.
Of course function mips32_pracc_clean_text_jump() must add this additional instructions (NOPs).
Only tested on bcm3348..
Change-Id: I3183d3ce865d469d7262ba4b15446e5743a5f1df Signed-off-by: Salvador Arroyo <salvador@telecable.es>
Reviewed-on: http://openocd.zylin.com/2270 Tested-by: jenkins Reviewed-by: Kent Brinkley <jkbrinkley.imgtec@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tomas Vanek [Sun, 15 Mar 2015 18:09:15 +0000 (19:09 +0100)]
target: improve robustness of reset command
Before this change jim_target_reset() checked examined state of a target
and failed without calling .assert_reset in particular target layer
(and without comprehensible warning to user).
Cortex-M target (which refuses access to DP under active SRST):
If connection is lost then reset process fails before asserting SRST
and connection with MCU is not restored.
This resulted in:
1) A lot of Cortex-M MCUs required use of reset button or cycling power
after firmware blocked SWD access somehow (sleep, misconfigured clock etc).
If firmware blocks SWD access early during initialization, a MCU could
become completely inaccessible by SWD.
2) If OpenOCD is (re)started and a MCU is in a broken state unresponsive
to SWD, reset command does not work even if it could help to restore communication.
Hopefully this scenario is not possible under full JTAG.
jim_target_reset() in target.c now does not check examined state
and delegates this task to a particular target. All targets have been checked
and xx_assert_reset() (or xx_deassert_reset()) procedures were changed
to check examined state if needed. Targets except arm11, cortex_a and cortex_m
just fail if target is not examined although it may be possible to use
at least hw reset. Left as TODO for developers familiar with these targets.
cortex_m_assert_reset(): memory access errors are stored
instead of immediate returning them to a higher level.
Errors from less important reads/writes are ignored.
Requested reset always leads to a configured action.
arm11_assert_reset() just asserts hw reset in case of not examined target.
cortex_a_assert_reset() works as usual in case of not examined target.
Change-Id: I84fa869f4f58e2fa83b6ea75de84440d9dc3d929 Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2606 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tomas Vanek [Sat, 19 Dec 2015 11:34:31 +0000 (12:34 +0100)]
flash Kinetis: new KVx family added
Cortex-M0+ and M4 motor control MCUs KV10, KV11, KV30, KV31,
KV42, KV44 and KV46 added to SDID identification.
Watchdog disable code changed to work on Cortex-M0+ (KV1x)
Protection size set to 1K for 16K flash devices (KV10Z16)
- cherry picked from Andrey Smirnov's change #2051
Change-Id: Ia6f4868eaf7e2cb6ad6a736210c703a67e0027be Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3235 Tested-by: jenkins Reviewed-by: Kyle Manna <kyle.manna@fuel7.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Peter D. Gray [Wed, 20 Apr 2016 17:02:48 +0000 (13:02 -0400)]
Add support for Atmel AT91SAMD21E16B (B variant) and a spelling mistake.
Change-Id: I55ab830aed34a02c53f3419facc81c7354368e30 Signed-off-by: Peter D. Gray <peter@conalgo.com>
Reviewed-on: http://openocd.zylin.com/3422 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Andreas Färber <afaerber@suse.de>
RTOS support: Correction of out of bound access of thread array
FreeRTOS use an array to store ready task. The array size is
configMAX_PRIORITIES. In the current implementation, the code try to access 1 more priority if the helper from freeRTOS contrib is used.
This has effect of detecting bad thread. This patch correct this and have been tested on
a code with more than 12 task.
Change-Id: Id229f0b2c4bf1aab87a2a69be174cc9b6dda00cb Signed-off-by: Jonathan Dumaresq <jdumaresq@cimeq.qc.ca>
Reviewed-on: http://openocd.zylin.com/3400 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Add new structure for for working with FPU thread in thread view.
This modification support both stacking.
When FPU is activated, LR must be validated to check if the FPU
register are push on the stack. This is mandatory to find the correct
stack pointer position.
cortex_a: allow physical memory access through AHB-AP again
This feature is required for boards that use a programmatical way
to reset the cpu, like the TI Pandaboard with OMAP4. The board only
has a 14 pin JTAG header that doesn't feature SRST and is reset by
direct write to the PRM_RSTCTL register.
iMX6 can be reset through triggering the on-chip watchdog, but for these
methods to work reliably, access through the AHB-AP without interaction
with the CPU core is necessary.
This patch adds a 'ftdi_location' command to select an adapter by usb
bus number and port path.
This is helpful if you have a rack full of adapters in a testing or
manufacturing setup where the only constant is the physical usb bus
location of the adapter you want to address. Vid:Pid are not unique,
serial number _may_ be unique (and maybe not with embedded adapters) but
will change when a new target is plugged.
Specifying a location allows to understand instantly which board failed
bringup or testing.
Linus Walleij [Tue, 12 Jan 2016 09:46:07 +0000 (10:46 +0100)]
armv4_5: support weirdo ARMv6 secure monitor mode
On the ARM PB1176JZF-S the system comes up in secure monitor
mode after reset. However the modebits in CPSR form the value
28 (0x1c) and CPSR is 0x800001dc deeming it UNRECOGNIZED.
Define this mode to be synonymous to mode 22 (MON) and things
start to work like a charm.
Change-Id: I001f7773ee1076202c0c633e466d2d833f7a1413 Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-on: http://openocd.zylin.com/3196 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Andreas Färber [Sun, 29 Nov 2015 02:09:46 +0000 (03:09 +0100)]
xmc4xxx: Integrate build of erase check code
Instead of pointing to the assembler sources in a comment and
inline-commenting the THUMB bytecode, place the hex array alongside the
assembler sources and include it via preprocessor.
Originally inspired by a typo in the file path during driver development,
but it also facilitates making changes to the assembler sources.
A Makefile is provided to help automate updating the bytecode. It is not
integrated with the automake system to avoid forcing an ARM cross-compiler
onto every user, i.e. after modifying the sources they need to be rebuilt
in that directory before building the usual way. ARM_CROSS_COMPILE= can
be passed on the make command line to deal with native ARM toolchains
or with varying prefixes of cross-toolchains.
Change-Id: I00ceb980a68c8554a180dd13719ac77b677a8bcd Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3133 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Andreas Färber [Mon, 20 Apr 2015 00:51:23 +0000 (02:51 +0200)]
flash: New Spansion FM4 flash driver
The Spansion FM4 family of microcontrollers does not offer a way to
identify the chip model nor the flash size, except for Dual Flash vs.
regular layout. Therefore the family is passed as argument and
wildcard-matched - MB9BFx6x and S6E2CC families are supported.
Iterations showed that ...
1) Just doing the flash command sequence from SRAM loader code for each
half-word took 20 minutes for an 8 KB block.
2) Doing the busy-wait in the loader merely reduced the time to 19 minutes.
3) Significant performance gains were achieved by looping in loader code
rather than in OpenOCD and by maximizing the batch size across sectors,
getting us down to ~2 seconds for 8 KB and ~2.5 minutes for 1.1 MB.
(Tested with SK-FM4-176L-S6E2CC-ETH v11, CMSIS-DAP v23.)
gcc, objcopy -Obinary and bin2char.sh are used for automating the
integration of hand-written assembler snippets.
Change-Id: I092c81074662534f50b71b91d54eb8e0098fec76 Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2190 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Alexander Kurz [Sun, 28 Feb 2016 11:36:19 +0000 (12:36 +0100)]
tcl/target/stm32f4: fix: reduce adapter speed before reset
The reset-init hook for this target speeds up the CPU clock and JTAG adapter
speed. When the target is reset running with high adapter speed, a series of
warnings "DAP transaction stalled (WAIT) - slowing down" will be generated
since the adapter speed is not reduced to fit the slower CPU speed.
Fix: reduction of the adapter speed before a reset is performed.
Change-Id: Iabfc8e3f70311e0e71c8eed09b8a37fcbed9c58d Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3365 Tested-by: jenkins Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Alexander Kurz [Fri, 26 Feb 2016 20:54:22 +0000 (21:54 +0100)]
arm_disassembler: bugfix, MRRC instruction not recognized
A copy-and-paste error in the arm_disassembler opcode evaluation
disabled the recognition of MRRC instructions.
According to the arm architecture ref. manual issue E or later, MRRC and MCRR
instructions are identified by opcode bits 20-27: MCRR = 0xc4, MRRC = 0xc5.
Error found by static code analysis using a semantic pattern to
detect duplicated tests xand.cocci, see coccinellery.org
Change-Id: Ic41426edb51c6816e11dc3d35ef9382ab34af486 Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3363 Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
projects / openocd / log