Matej Kupljen [Wed, 11 Feb 2015 08:28:41 +0000 (09:28 +0100)]
gdb_server: ignore stray + in ACK mode
I couldn't make OpenOCD to work with GDB. I was always getting this in GDB:
(gdb) target remote localhost:3333
Remote debugging using localhost:3333
Ignoring packet error, continuing...
Ignoring packet error, continuing...
Ignoring packet error, continuing...
Ignoring packet error, continuing...
Malformed response to offset query, timeout
(gdb)
While debugging gdb remote protocol, I have seen that gdb responds with:
w ++$?#3f
And those two '+' seems to confuse the OpenOCD parser, if it sees another
'+' sign it emits the DEBUG output and sets the noack_mode to 2. The
problem is that we weren't even IN noack mode, this was set to 0 and then
it explicitly sets it to 2 and thus turning the noack mode on.
Change-Id: If267c9226e57fa83121ded09cf69829f8f0b4b93 Signed-off-by: Matej Kupljen <matej.kupljen@gmail.com>
Reviewed-on: http://openocd.zylin.com/2545 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Cortex A: fix extra memory read and non-word sizes
Without this patch, to perform a memory read, OpenOCD first issues an
LDC instruction into DBGITR in Stall mode (thus executing the
instruction), then switches to Fast mode and reads from DBGDTRTX once
for each word to transfer.
At the very end of the transfer, the final Fast mode read of DBGDTRTX
has, as always, the side effect of re-issuing the LDC instruction. This
causes two problems:
(1) If the word immediately beyond the end of the requested region is
inaccessible, this spurious LDC will cause a fault. On a fast CPU, the
LDC will finish executing by the time the poll of DSCR takes place,
failing the entire memory read. On a slow CPU, the LDC might finish
executing later, leaving an unexpected and confusing sticky fault lying
around for the next operation to see.
(2) If the LDC succeeds, it will leave the loaded word in DBGDTRTX, thus
setting DBGDSCR.TXFULL=1. The cortex_a_read_apb_ab_memory routine
completes without consuming that last word, thus confusing the next
routine that tries to use DBGDTRTX (this may not have any visible effect
on some implementations, because writing to DBGDTRTXint when TXFULL=1 is
defined as Unpredictable, but I believe it caused a visible problem for
me).
With this patch, the bulk mem_ap_sel_read_buf_noincr is modified to omit
the last word of the block. The second-to-last read of DBGDTRTX by that
function will cause the issue of the LDC for the last word. After
switching back to Normal mode and waiting for that instruction to
finish, do a final read of DBGDTRTX to extract the last word into the
buffer, leaving TXFULL=0.
Without this patch, memory accesses are always expanded such that they
are aligned to the access size. With this patch, accesses are issued
exactly as ordered by the caller. The caller is expected to handle
fragments at the beginning and end of the transfer if the address is
unaligned and an unaligned access is not desired.
Without this patch, the DFAR and DFSR registers, which report the
location and status of data faults, are ignored while performing memory
accesses, which could cause problems debugging an OS page fault handler.
With this patch, DFAR and DFSR are preserved across memory accesses, and
DFSR is decoded in the event of a synchronous fault to provide the
caller with more information about the reason for failure.
Thanks to Boris Brezillon for the original patch whose ideas led to the
non-word access mechanism implemented here and to various code reviewers
for their comments.
Change-Id: I11ae7104fbe69a522efadefc705c9a217a7eef41 Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/2381 Tested-by: jenkins Reviewed-by: Olivier Schonken <olivier.schonken@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Andrej Kazmin [Fri, 22 Aug 2014 07:35:06 +0000 (11:35 +0400)]
flash/nor/at91samd: add small delay before checking nvm status
OpenOCD's SWD subsystem doesn't currently have a consistent WAIT
handling (i.e. it doesn't ever retry, just returns an error), so right
after a row write a small delay is needed as AHB access is stalled
during the flashing operation.
The issue was exposed with a samd20 using ftdi SWD transport.
Change-Id: I07d99d3a96845cc689c3904a41f4d41344f200aa Signed-off-by: Andrej Kazmin <funnyfish@funnyfish.botik.ru> Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2268 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Paul Fertser [Fri, 23 Jan 2015 08:38:31 +0000 (11:38 +0300)]
flash/startup: extend "program" command to accept "exit"
This optional argument tells OpenOCD to exit after finishing (either
succesfully, or with an error) the programming sequence. Without it
OpenOCD stays running.
Change-Id: I6ecaf33ff985eea9a9cd02ff644a74403ae3e1e5 Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2492 Tested-by: jenkins Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Paul Fertser [Tue, 27 Jan 2015 18:10:18 +0000 (21:10 +0300)]
server: shutdown command should lead to exit without evaluating the rest
Currently
openocd -c "echo a1; shutdown; echo a2"
outputs both "a1" and "a2" and only then shuts down. This patch fixes
it by making shutdown command throw an exception, so unless it's
caught the shutdown will behave as expected.
Change-Id: I764268b3a9046ff3e9717d04095ea0673f1d755a Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2511 Tested-by: jenkins Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The registers are represented as bit arrays intended to be accessed using
the buf_set_* and buf_get_* functions. Storing the register values in
integers enables accessing them directly, which gives different results
depending on host byte order.
Convert the register store to use a byte array instead and fix all the
byte order bugs uncovered by that.
Also merge the 32 and 64 bit register fields. Only one of them is used at
a time and after the change to byte arrays their types are also the same.
Change-Id: I456869a1737f4b4f5e8ecbfc1c63c49a75d21619 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2475 Tested-by: jenkins Reviewed-by: Hsiangkai Wang <hsiangkai@gmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
sim3x: new flash driver for Silabs SiM3 microcontroller family
This is a new driver for Silicon Laboratories SiM3 microcontroller
family, based on the work of Ladislav Bábel. The driver will try to
detect the type of MCU from the device id register, and if this
fails it will use the flash size from the flash bank command.
Driver added to the documentation and to the README.
TCL script added.
Tests:
* Hardware: SiM3C166 (pre-production) and SiM3U167
* Binary: 4kb, 197kb, 256kb
* Flash protect not tested
Change-Id: I701e0cf505ca8ad99be7f83543fe5055b2f65dcc Signed-off-by: Andreas Bomholtz <andreas@seluxit.com> Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2078 Tested-by: jenkins
Daniel Glöckner [Thu, 20 Nov 2014 22:57:26 +0000 (23:57 +0100)]
armv7a: fix interpretation of MMU table
On armv7 there no longer are 1kB pages. Instead the bit that in
older architectures distinguished 1kB pages from 4kB pages is on
armv7 used for as execute-never marker. There may now also be 16MB
supersections with 40 bit physical address.
Change-Id: I959bdb8012782a9d07d968907a21f50e3d9b356a Signed-off-by: Daniel Glöckner <daniel-gl@gmx.net>
Reviewed-on: http://openocd.zylin.com/2386 Tested-by: jenkins Reviewed-by: Vladimir Svoboda <ze.vlad@gmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Jose de Sousa [Wed, 11 Jun 2014 23:05:20 +0000 (00:05 +0100)]
target: write gmon.out according to target endianness
After profiling gmon.out was being written in little endian format only
which would cause gprof to issue and error and exit on big endian targets.
Change-Id: I526a40adae0f9a439fc5b77cef30fda228198b48 Signed-off-by: Jose de Sousa <jose.t.de.sousa@gmail.com>
Reviewed-on: http://openocd.zylin.com/2168 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Pawel Si [Sat, 6 Dec 2014 16:31:18 +0000 (17:31 +0100)]
mini51: support for Nuvoton NuMicro M051 series flash memory
adds flash support for Nuvoton M052, M054, M058, M0516 microcontrollers
into the mini51 driver, patch also adds support for programing LDROM,
flash data and flash config.
I've tested it on a M0516LBN microcontroller using an ST-LINK/V2:
1. removing security lock:
openocd -f interface/stlink-v2.cfg -f target/m051.cfg -c "init ; halt ; mini51 chip_erase; exit"
2. flashing:
openocd -f interface/stlink-v2.cfg -f target/m051.cfg -c "program file.hex"
Change-Id: I918bfbb42461279c216fb9c22272d77501a2f202 Signed-off-by: Pawel Si <stawel+openocd@gmail.com>
Reviewed-on: http://openocd.zylin.com/2426 Tested-by: jenkins Reviewed-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Jacob Palsson [Tue, 29 Jul 2014 12:36:40 +0000 (14:36 +0200)]
tcl/target: add CC2538 and CC26xx target files (with cJTAG procedure)
Added support for the Cortex-M3 based TI low power RF SoC CC2538 and
the CC26xx family.
These chips need a start sequence for switching from cJTAG to JTAG
before being used with OpenOCD, this is done in the tcl proc
ti_cjtag_to_4pin_jtag in the ti-cjtag.cfg config.
The configs for CC2538 and CC26xx run the start sequence on post-reset
event and set the ICEPick IDCODE in the data register for OpenOCD to
read, this is done so that every time OpenOCD resets the device, it
will enable JTAG.
Change-Id: I7db620211c0e7e03fad59d24fe31d23a9cdcfedc Signed-off-by: Jacob Palsson <jaaacke@gmail.com>
Reviewed-on: http://openocd.zylin.com/2232 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Michael Brown [Thu, 15 Jan 2015 15:35:21 +0000 (10:35 -0500)]
lpc2000: add chip IDs for LPC11U6x/LPC11E6x
Change-Id: I53568674951ec8a5db5e191c7b50c60b5a84d0b6 Signed-off-by: Michael Brown <fractalmbrown@gmail.com>
Reviewed-on: http://openocd.zylin.com/2463 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tomas Vanek [Mon, 8 Sep 2014 08:34:10 +0000 (10:34 +0200)]
psoc4: support for Cypress PSoC 41xx/42xx family
New NOR flash driver was derived from stm32lx.
Procedure ocd_process_reset_inner is overriden in psoc4.cfg
to handle reset halt and system ROM peculiarities.
Change-Id: Ib835324412d106ad749e1351a8e18e6be34ca500 Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2282 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Jussi Kivilinna [Wed, 17 Dec 2014 10:14:32 +0000 (12:14 +0200)]
stm32lx: do not attempt mass-erase in-place of first bank erase
Commit 832f0a5bfb439 'stm32: add mass erase support for STM32L' added
use of mass-erase in-place of bank-erase. This is triggered if first
bank is requested to be fully erased.
This erroneous action completely fails on STM32L162VEY (has 512 KiB
flash in two 256 KiB banks) and also unintently destroying contents of
EEPROM and second flash bank.
Change-Id: I0f13f7b0346747a09c755d72b5b95775ceff5a6f Signed-off-by: Jussi Kivilinna <jussi.kivilinna@haltian.com>
Reviewed-on: http://openocd.zylin.com/2441 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
Paul Fertser [Fri, 23 Jan 2015 09:33:50 +0000 (12:33 +0300)]
flash/nor/stm32l: fix mass erase
Topaz reports on http://sourceforge.net/p/openocd/tickets/87/ that
protection level constants are mixed up. This leads to device ending
up in protection level 1 after mass erase.
Additional work is required to actually put the device in RDP Level 1
and then back to Level 0, as Option bootloader launch is a special
kind of full target reset.
To be able to flash properly after mass_erase a "reset init" is needed
(it's anyway recommended to always perform it before any flash
operation).
Change-Id: I9a838909458039bb0114d3019723bf134fa4d7c9 Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2490 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Paul Fertser [Tue, 20 Jan 2015 17:09:02 +0000 (20:09 +0300)]
configure: define WIN32_LEAN_AND_MEAN early to make it effective
This macro makes windows builds faster and helps with the old "#define
interface struct" issue as the word "interface" is part of libusb-0.1
API. However, defining it in replacements.h is too late, as windows.h
gets included by that time from somewhere else.
This solution is provided by Ray Donnelly from the MSYS2 team.
Change-Id: I376a5fb3d106786515d7e1ba44dbd751e4dcdb1b Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2486 Tested-by: jenkins Reviewed-by: Xiaofan <xiaofanc@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Paul Fertser [Tue, 20 Jan 2015 15:29:31 +0000 (18:29 +0300)]
Makefile.am: link libusb-1.0 after libusb-0.1 to fix dependencies
Since libusb-0.1 might be provided by libusb-compat, it will depend on
libusb-1.0, so needs to be mentioned before it in the link command
line, this is relevant for static linking.
Thanks go to mingwandroid for spotting it during MSYS2 build.
Change-Id: I15cf0b8f084c351b4f93e75686bd0f843477352b Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2485 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Paul Fertser [Sat, 17 Jan 2015 12:15:11 +0000 (15:15 +0300)]
Use (uint8_t *) for buf_(set|get)_u(32|64) instead of (void *)
This helps to uncover incorrect usage when a pointer to uint32_t is
passed to those functions which leads to subtle bugs on BE systems.
The reason is that it's normally assumed that any uint32_t variable
holds its value in host byte order, but using but_set_u32 on it
silently does implicit pointer conversion to (void *) and the
assumption ends up broken without any indication.
Change-Id: I48ffd190583d8aa32ec1fef8f1cdc0b4184e4546 Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2467 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Jens Bauer [Fri, 16 Jan 2015 22:57:09 +0000 (23:57 +0100)]
stm32f2x: Fix byte order bug.
Do not use buf_set_u32 on integers; they're not buffers.
If using buf_set_u32 on integers, bytes will be exchanged on Big Endian targets.
In this particular case, FLASH_OPTCR was incorrectly written, causing it to often
contain one of these values: 0x00aaaae1, 0x00aaffef, 0x00ffabe1 or 0x00abffe1.
This write-protected the device before flash-programming, causing this command...
flash write_image erase unlock myfile.elf
... to fail, complaining about write-protection.
Repeating the above command would change the OPTCR register each time.
After applying this patch, the OPTCR remains "unchanged".
Enable auto-creating additional discovered TAPs even if some TAPs are
predefined, avoiding initialization failure when it's not necessary.
Also, drop the arbitrary limit on the number of predefined TAPs. Still,
don't auto-create any if there are more than 20 TAPs already, to stop
a noisy connection from creating unlimited TAPs.
Create auto-probed TAPs with less noise.
Reduce code duplication between verification and auto-probing.
Change-Id: I82a504d92dbcc0060206e71f10c5158256b5f561 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2236 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Jaakko Kukkohovi [Wed, 21 Jan 2015 14:16:31 +0000 (16:16 +0200)]
jtag/drivers/cmsis-dap-usb: fix cmsis_dap_serial
Previously the serial wasn't actually used in hid_open() call,
which meant that the first device with matching vid:pid was opened
irrespective of the actual serial number.
Change-Id: I45216ae5d9e0798e97be693c30e2f03c89b9a02b Signed-off-by: Jaakko Kukkohovi <jkukkohovi@gmail.com>
Reviewed-on: http://openocd.zylin.com/2487 Tested-by: jenkins Reviewed-by: Jörg Wunsch <openocd@uriah.heep.sax.de> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Spencer Oliver [Thu, 9 Oct 2014 19:08:23 +0000 (20:08 +0100)]
stlink: add reconfigurable speed support
The ability to change the speed has been added to firmware versions J22 and
above. Any attempt to change on earlier versions will be ignored without error,
as the existing code does.
For supported firmware versions the driver will attempt to get as close as
possible to supported speeds (never higher).
The default stlink speed on power up is 1.8MHz.
The driver will now also print supported clocl speeds during init.
Change-Id: Iee9bd018bb8b6f94672a12538912d41c23d48a7e Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/2335 Tested-by: jenkins
Nemui Trinomius [Thu, 18 Dec 2014 23:24:25 +0000 (08:24 +0900)]
lpc2000: Improve lpc2000 flash driver.
This patch adds flash programming support for LPC5410x and LPC82x.
And adds auto flash size detection for LPC800 series.
Tested on below listed boards/chips.
LPC54102(LPCLPC54102Xpresso)
LPC824(LPCXpresso824-MAX)
LPC812(LPC812MAX)
LPC811,LPC810
Change-Id: Ie68b6d425b17ccfa83814607ee61056e99800c1c Signed-off-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp>
Reviewed-on: http://openocd.zylin.com/2442 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Kamal Dasu [Thu, 29 Aug 2013 18:02:19 +0000 (14:02 -0400)]
cortex_a: Add support for A15 MPCore
Added Cortex-A15 support for DAP AHB-AP init code as per ADI V5 spec.
Also added changes to make the APB MEM-AP to work with A15.
Made the the cortex_a target code generic to work with A8, A9
and A15 single core or multicore implementation. Added armv7a code
for os_border calculation to work for known A8, A9 and A15
platforms based on the ARM DDI 0344H, ARM DDI 0407F, ARM DDI 0406C
ARMV7A architecture docs.
Change-Id: Ib2803ab62588bf40f1ae4b9192b619af31525a1a Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Reviewed-on: http://openocd.zylin.com/1601 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Paul Fertser [Sun, 2 Nov 2014 12:16:13 +0000 (15:16 +0300)]
swd: handle various failure conditions
When communication with target fails for whatever reason, it makes
sense to do JTAG-to-SWD (in case the target got power-cycled or the
DAP method was reset anyhow), SWD line reset sequence (part of
JTAG-to-SWD already) and the mandatory IDCODE read. Schedule that to
be performed on the next poll.
Fix the return values for ftdi and jlink drivers to be consistent with
OpenOCD error codes and remove ad-hoc calls to perform DAP method
switching (as it's now done from the upper layer automatically).
Change-Id: Ie18797d4ce7ac43d8249f8f81f1064a2424e02be Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2371 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Mateusz Manowiecki <segmentation@fault.pl>
Paul Fertser [Sun, 2 Nov 2014 12:03:16 +0000 (15:03 +0300)]
target: improve robustness of polling and reexamination
When a target was present on OpenOCD start but later disappeared for
whatever reason (typically unstable connection or target going to
sleep) and reappeared only for a brief period of time, reexamination
would fail, and poll would no longer run. This patch fixes it.
Change-Id: I61f9b5a3f366a761320e233f4e1689f926b5556d Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2370 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
Paul Fertser [Thu, 27 Nov 2014 07:54:07 +0000 (10:54 +0300)]
checkpatch: fix check for the FSF address
Commit 4525c0a4c4d0aaa199c37a6d2245617e8445f213 cherry-picked check
for the FSF address presence from upstream. However, it has a typo
resulting in this obscure error when triggered:
Use of uninitialized value in concatenation (.) or string at /home/jenkins/.jenkins/jobs/openocd-gerrit/workspace/tools/scripts/checkpatch.pl line 1258.
ERROR:
This patch fixes it.
Change-Id: Ia417ef4782d21c8b3f1d39de88c4ab850a5a6630 Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2414 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Karl Palsson [Fri, 21 Nov 2014 22:14:57 +0000 (22:14 +0000)]
stm32l: split l0/l1 support no jtag, different HSI settings
L0 is cortex m0+, so different id codes, SWD only, different addresses
for the clock speedup. It has no endian options, no boundary scan.
Removed all L0 specific portions from L1 files, and renamed files to clarify
their purpose. The deprecated stm32lx_stlink.cfg is kept as is, as it is only
around for backwards compatibility with prior releases.
Tested on STM32L053 Discovery and STM32L151 Discovery.
Has _not_ been tested with jtag on L1.
Change-Id: I8eea890d2f92a302d9e9c8a8832d218ee1b6bcfc Signed-off-by: Karl Palsson <karlp@tweak.net.au> Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2405 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Juha Niskanen <juha.niskanen@haltian.com>
Grigori Goronzy [Thu, 30 Oct 2014 00:14:58 +0000 (01:14 +0100)]
lpc2000: ignore status of part ID IAP command
The IAP firmware won't return a proper status with some versions. This
happens on my CCC r0ket board and others have seen it as well [1]. So
just ignore the status code and do a (weak) consistency check instead.
projects / openocd / log