Ake Rehnman [Sat, 21 Jan 2017 09:42:11 +0000 (10:42 +0100)]
jtag/drivers/stlink_usb : implemented and repaired SWIM support
Fixed a bug in stlink_usb_read_mem/write_mem preventing large data transfers
The SWIM support in stlink_usb was basically non existent so I have
implemented the missing parts. The bCBWCBLength and dCBWDataTransferLength
for STLINK-V1 protocol was not correct so that was fixed. The reason for
adding SWIM support is to add STM8 support for OpenOCD.
I have tested the driver on:
STM8 discovery board with the built-in STLINK-V1
STM8 discovery board with STLINK-V2 dongle
STM32 vldiscovery board with the built-in STLINK-V1
STM32F1xxx processor with STLINK-V2 dongle
Change-Id: I4aa80a92fb0226174356adaf2f8ff949920a621f Signed-off-by: Ake Rehnman <ake.rehnman@gmail.com>
Reviewed-on: http://openocd.zylin.com/3952 Tested-by: jenkins Reviewed-by: Philipp Klaus Krause Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Functions mem_ap_read() and mem_ap_write() incremented address even
if addrinc=false. I overlooked this fact and moved mem_ap_setup_tar()
set wrong addresses in no-incr mode.
Fixed by preventing address increment in no-incr mode.
Change-Id: I512e12a6a64e30cf6bc5bf77e3d57d35cc33e058 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Suggested-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/4326 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tomas Vanek [Thu, 15 Jun 2017 09:03:32 +0000 (11:03 +0200)]
arm_adi_v5: reduce some CSW writes
MEM-AP access through banked data registers MEM_AP_REG_BD0..3
does not increment TAR regardless of the current autoincrement mode.
mem_ap_read_u32() and mem_ap_write_u32() can keep the current
autoincrement mode instead of switching autoincrement off.
Change-Id: Ib7ec688d3e04f1da678363cd2819ce90e8910e58 Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4163 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tomas Vanek [Thu, 15 Jun 2017 06:59:01 +0000 (08:59 +0200)]
arm_adi_v5: fix wrong addressing after change of CSW_ADDRINC
Problem: If the same memory location is accessed alternatively
by MEM-AP banked data registers without autoincrement and by standard
autoincremented read/write, TAR register is not updated correctly.
How to replicate: On a Cortex-M issue
mdw 0xe000edf0
multiple times. When poll is on (poll reads the same memory location)
only the first read is correct.
0xe000edf0: 01000000
0xe000edf0: 00000000
0xe000edf0: 20002640
0xe000edf0: 01000000
0xe000edf0: 00000000
0xe000edf0: 00000000
mem_ap_setup_tar() writes to MEM_AP_REG_TAR if requested TAR value
changed or CSW_ADDRINC_... is currently active.
However if an autoincremented access has been issued and autoinc
switched off in CSW afterwards, TAR does not get updated.
The change introduces mem_ap_update_tar_cache() which is called
after queuing of any access to MEM_AP_REG_DRW. It simulates
TAR increment to keep tar_value in sync with MEM_AP.
Crossing tar autoincrement block boundary invalidates cached value.
mem_ap_write() and mem_ap_read() do not check tar autoincrement
block boundary, mem_ap_setup_tar() is called before each transfer instead.
dap_invalidate_cache() is introduced to ensure invalidation
of all cached values during dap_dp_init() and swd_connect()
Change-Id: I815c2283d2989cffd6ea9a4100ce2f29dc3fb7b4 Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4162 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Bas Vermeulen [Sun, 26 Nov 2017 21:31:55 +0000 (22:31 +0100)]
target aarch64: rework memory read/write to use 8/16/32 bit operations
The existing code only used Memory Access mode to read memory,
which uses 32 bit operations only.
Rework the code to check the alignment/size of the read/write operation,
and use the Memory Access mode to read aligned 32 bit memory.
When using unaligned access, or 8 or 16 bit reads, use LDR{BHW} and STR{BHW}
instead.
The exception handling is still the same as it was before (meaning it breaks
when things go wrong), but I can now read an 8 bit register correctly.
Change-Id: I739a5ee825c0226ed4a89c32895cc2a047b8dc15 Signed-off-by: Bas Vermeulen <bas@daedalean.ai>
Reviewed-on: http://openocd.zylin.com/4301 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tomas Vanek [Sun, 9 Apr 2017 08:59:57 +0000 (10:59 +0200)]
jtag/drivers/cmsis-dap: fix connect under reset
Commit ef02b69b14d133b061217a91add5a028a77e86bc included
a call to cmsis_dap_cmd_DAP_Connect() before calling
cmsis_dap_cmd_DAP_SWJ_Sequence(). According to comment
it is necessary for at least Keil ULINK-ME.
Commit 72c3464be42088dc75245cf2fcc8f5c6e6959b4b added
a cmsis_dap_cmd_DAP_Disconnect() before connect call to pair
connection/disconnection. It solves some problems on Atmel EDBG.
Unfortunately calling either of cmsis_dap_cmd_DAP_Connect()
or cmsis_dap_cmd_DAP_Disconnect() deasserts reset signal.
So these workarounds break ability to connect under reset.
Use cmsis_dap_cmd_DAP_Disconnect() and cmsis_dap_cmd_DAP_Connect()
pair only if both SRST and TRST are deasserted.
Change-Id: I0914dae0a1360b8c7fe48231ff3867caedfb2dbe Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reported-by: Leonardo Sabino dos Santos <leonardo.sabino@gmail.com>
Reviewed-on: http://openocd.zylin.com/4100 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tomas Vanek [Thu, 23 Nov 2017 13:47:37 +0000 (14:47 +0100)]
flash/nor/stm32f2x: fix erase on STM32F413/423
Theese devices do not have a gap in sector numbering.
The driver translates sectors numbers 12 13... to 16 17... as used on dual
bank flash devices. Therefore erase of sector 12 and above fails with error
'stm32x device protected'
on F413/423.
Drop sector number translation for devices without has_large_mem flag.
Change-Id: I65531c0dfe02e2fd0f3d68f0615e0926e9901391 Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4299 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tomas Vanek [Thu, 26 Oct 2017 16:00:33 +0000 (18:00 +0200)]
flash/nor/stm32f2x: fix protection block size for F767 in dual bank mode
A protection block comprises two adjacent sectors in dual bank mode.
As there are 64 and 128kB sectors joined in blocks 2 and 8, block size
should be computed as a sum of sector sizes.
Change-Id: Ie915df8cf7ca232c4565d7e0c514c8933e71fdfe Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4271 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Ake Rehnman [Mon, 6 Nov 2017 18:56:28 +0000 (19:56 +0100)]
stm8 : new target
New STM8 target based mostly on mips4k. Target communication
through STLINK/SWIM. No flash driver yet but it is still possible
to program flash through load_image command. The usual target debug
methods are implemented.
Change-Id: I7216f231d3ac7c70cae20f1cd8463c2ed864a329 Signed-off-by: Ake Rehnman <ake.rehnman@gmail.com>
Reviewed-on: http://openocd.zylin.com/3953 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Bas Vermeulen [Tue, 21 Nov 2017 16:12:24 +0000 (17:12 +0100)]
Only call cmsis_dap_cmd_DAP_SWD_Configure when swd_mode is enabled
The CMSIS-DAP used by NXP's LS1012ARDB board only supports JTAG,
and not SWD. Calling cmsis_dap_cmd_DAP_SWD_Configure returns with an
error (and doesn't actually do anything in the debugger).
Wrap the call to cmsis_dap_cmd_DAP_SWD_Configure in a check for
swd_mode, to make sure initialisation doesn't fail needlessly.
Change-Id: Id7e568cb6e36886bd7c5b3699d198a77a51c28c9 Signed-off-by: Bas Vermeulen <bas@daedalean.ai>
Reviewed-on: http://openocd.zylin.com/4294 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Robert Jordens [Fri, 19 Aug 2016 21:49:49 +0000 (05:49 +0800)]
spi: add n25q256 flash
* 256 MBit SPI flash
* https://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qljs_l_256_aba_0.pdf spells out the entire zoo of IDs
* used e.g. on Xilinx KCU105
Change-Id: I18b19292b4869627adb9071266271962fec68fb4 Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/4186 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Marc Schink [Sun, 29 Oct 2017 14:58:41 +0000 (15:58 +0100)]
target: Constify parameter of is_armv7m()
Change-Id: Ieea1b0dec88818e9e8d5c8c5d54aa8959556d77b Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4275 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Jonas Norling [Wed, 25 Oct 2017 09:33:06 +0000 (11:33 +0200)]
ftdi: Enable SWDIO output before sending data on it
The SWDIO buffer has to be enabled, by setting SWDIO_OE, for data on
SWDIO to reach the target. Explicitly do this before sending the
switch sequences for JTAG-to-SWD, etc.
This makes the code insensitive to the state of SWDIO_OE specified in
ftdi_layout_init. It used to work only on adapters with a non-inverted
SWDIO_OE inited to 1, or inverted SWDIO_OE inited to 0.
Change-Id: I4b9e520ac1c7ce2a437251a05fc036bc68de718e Signed-off-by: Jonas Norling <jonas.norling@cyanconnode.com>
Reviewed-on: http://openocd.zylin.com/4270 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Similar to the Sheevaplug fix inf95f8b70fbd0f7e9c91a2d9006b1abb2dd07ebf2
the OpenRD device has its JTAG interface on the first channel of the
ft2232, which is 0 for the new driver but was 1 for the old one. Correct
the config file appropriately. Also the device description was missing
the trailing " B" and thus not picking up the device correctly. Finally
add an adapter_khz setting in the OpenRD board configuration file - set
to 2MHz to match the Sheeva variant.
Confirmed as working thanks to Phil Hands providing me access to his
hardware to test on.
See also Debian Bug#793214; https://bugs.debian.org/793214
Change-Id: Ifacf53124eaa330bbbdf36dfa79e3256bf2a5201 Signed-off-by: Jonathan McDowell <noodles@earth.li>
Reviewed-on: http://openocd.zylin.com/4254 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The dhcsr_save variable was used to save the value of
cortex_m->dcb_dhcsr so it could be restored later. However, all writes
in between the save and the restore use mem_ap_write_atomic_u32, not
cortex_m_write_debug_halt_mask, which means cortex_m->dcb_dhcsr isn’t
changed anyway. Delete the unnecessary local.
Change-Id: I064a3134e21398e1ecfc9f1fa7efd7b020b52341 Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4240 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
In cortex_m_assert_reset, in two locations, DHCSR is written directly
using mem_ap_write_u32. This means that the cached version,
target_to_cm(target)->dcb_dhcsr, is not updated when these writes are
performed, so subsequent writes to DHCSR that use
cortex_m_write_debug_halt_mask will change those bits back to their old
values which, unless modified in that particular invocation, come from
the cache. This causes an actual, observable bug on an STM32F7 in which
running “reset run” immediately after “program” can in some cases result
in execution proceeding with C_MASKINTS set (it is cleared on line 1021
but is then set immediately afterward in cortex_m_clear_halt), causing
failure of the application. Replace these mem_ap_write_u32 calls with
cortex_m_write_debug_halt_mask calls to do the same jobs.
Change-Id: Id35ca7f6057c2df2ba9cd67c53a73b50816d0b71 Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4239 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Freddie Chopin [Thu, 29 Jun 2017 21:49:03 +0000 (23:49 +0200)]
Fix GCC7 warnings about string truncation
GCC7 with -Wall warns about possible string truncation with
snprint()-type functions with "directive output may be truncated writing
1 byte into a region of size between 0 and 9
[-Werror=format-truncation=]" + "note: ‘snprintf’ output between 5 and
14 bytes into a destination of size 12" (or similar). Fix this by
increasing sizes of buffers.
See https://gcc.gnu.org/gcc-7/changes.html
Change-Id: Ib848f2a56dd658783534158947ae1be7c0e99d45 Signed-off-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-on: http://openocd.zylin.com/4175 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Freddie Chopin [Thu, 29 Jun 2017 21:48:19 +0000 (23:48 +0200)]
Fix GCC7 warnings about switch-case fallthroughs
GCC7 with -Wextra warns about switch-case blocks which fallthrough with
"this statement may fall through [-Werror=implicit-fallthrough=]". This
can be fixed by adding "special" comments: "/* fallthrough */".
Peter Griffin [Mon, 12 Jun 2017 15:28:03 +0000 (16:28 +0100)]
tcl: add hi3798 target and Tocoding Poplar board config
This config covers the 4x Cortex A53 CPUs. A custom connector
is required from J14 to standard ARM JTAG on v1 boards. However
v2 hardware should have a standard FTSH-105-01-L-DV connector.
Pinmuxing code to enable JTAG pins is included in l-loader-poplar
repository, so board is flashed with open source code, JTAG
is available at very early boot. Alternatively the following
pokes can be issued from U-Boot to enable JTAG (e.g. to debug
hisilicon SDK).
Uwe Bonnes [Mon, 14 Nov 2016 18:12:38 +0000 (19:12 +0100)]
stm32lx.c: Read IDcode at appropriate address.
Trying to read the L0 idcode at the L1 idcode address 0xE0042000 often
resulted in an uncatched error. Reading at the right L0 address 0x40015800
afterwards results in reading 0. So access to the device is denied..
Diego Herranz [Thu, 3 Aug 2017 06:37:41 +0000 (07:37 +0100)]
tcl/interface/ftdi: improve minimodule config
- Tested on a real FT2232H MiniModule, so warning removed.
- Every pin initially set to high impedance except TCK, TDI,
TDO and TMS: Safest values given it's an evaluation board
and the rest of pins might be connected to something else.
- Reset is now initially de-asserted (it was asserted
which is not recommended).
- nRST pin choice is arbitrary so comment added (wondering
if it should be an "echo").
- "-oe" option added to NRST signal so it can be set as
high impedance (tri-stated).
Change-Id: I967ab0c7bbccf72dbf6d6d78b3180b74e016e0d6 Signed-off-by: Diego Herranz <diegoherranz@diegoherranz.com>
Reviewed-on: http://openocd.zylin.com/4185 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The migration from the old ft2232 driver to the new generic ftdi driver
ended up breaking support for the SheevaPlug device. The old driver
defaulted to channel 1, but numbered the channels 1 to 4. The new driver
starts at 0. The SheevaPlug JTAG is on interface A (interface B is the
serial console), so it should be using channel 0. Fix this. Confirmed
as working; serial console remains available and a new u-boot image can
be transferred across using the JTAG link.
See also Debian Bug#837989; https://bugs.debian.org/837989
Change-Id: I4ac2bfeb0d1e7e99d70fa47dc55f186e6af2c542 Signed-off-by: Jonathan McDowell <noodles@earth.li>
Reviewed-on: http://openocd.zylin.com/4206 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
Marc Schink [Thu, 24 Aug 2017 15:42:28 +0000 (17:42 +0200)]
stm32f2x: Fix left shift of negative value
Use unsigned constant for left shift operation in order to avoid the
following error with GCC >= 6.0:
../src/flash/nor/stm32f2x.c: In function ‘stm32x_handle_unlock_command’:
../src/flash/nor/stm32f2x.c:1324:67: error: left shift of negative value [-Werror=shift-negative-value]
stm32x_info->option_bytes.optcr2_pcrop = OPTCR2_PCROP_RDP | (~1 << bank->num_sectors);
Change-Id: I0ac082bd0dbb8dc2f61ffff8fdf486ab7962d2e0 Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4207 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Anton Fosselius <anton.fosselius@gmail.com> Reviewed-by: Esben Haabendal <esbenhaabendal@gmail.com>
Karl Palsson [Wed, 10 May 2017 14:37:51 +0000 (14:37 +0000)]
telnet_server: increase buffer sizes to allow longer commands.
A common use case seen in the wild is echoing a string of commands to an
existing openocd instance via netcat. The sequence of ; separated
commands can easily run over the line limit of only 256 chars.
Increasing this dramatically reduces surprises, at the expense of a tiny
amount of extra ram usage.
Change-Id: I2389d99d316a96b5fa03f0894b43c412308e12c4 Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-on: http://openocd.zylin.com/4132 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Andreas Bolsch [Sun, 5 Mar 2017 18:01:06 +0000 (19:01 +0100)]
Support for STM32F722, F723, F413 and F423
IDs for STM32F722, F723, F413 and F423 added, handling of PCROP
for F722/723 and additional nWPRT bits for F413/423 implemented.
The additional protection bit positions for F413/423 conflict
with other options bits for the F7xx variants, additionally the
last two sectors share a common bit.
Protection for F413 and F767/777 now use protection blocks
rather sectors for dealing with protections bits.
Checking for halted state in 'lock' and 'unlock' removed: When
PCROP is activated in F723, halted state is not detected properly,
but lock/unlock sequence is required to disable PCROP.
Tested with STM32F723E-Disco, STM32F413ZH-Nucleo.
Change-Id: Ie6ddab47a9ae8461087d369b4f289b7f9d1e031c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/4045 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tomas Vanek [Thu, 13 Jul 2017 19:35:22 +0000 (21:35 +0200)]
flash Kinetis: fix probe for FlexNVM partitioned as EEPROM backup
If a MCU has FlexNVM partitioned as EEPROM backup only
(no data flash), kinetis_probe_chip() detects zero fcfg2_maxaddr1
and adjusts flash banks count to 1, what is obviously wrong.
The change limits the test to devices without FlexNVM.
Computation of program flash/FlexNVM blocks is now more robust.
Missing case 0x07 is added to switch (fcfg1_depart)
Change-Id: I0bd6030a0fe1ab62aeb0223bbdf2aee1505bf6a0 Reported-by: simon.haines@scalardata.com Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4180 Tested-by: jenkins Reviewed-by: Simon Haines <simon.haines@scalardata.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tomas Vanek [Thu, 29 Jun 2017 21:06:55 +0000 (23:06 +0200)]
flash Kinetis: fix devices with smallest program flash (8 and 16 kB)
Change-Id: I2692b9877a7f877104528f279a69e8cc1cfbcdbf Reported-by: David Miller Lowe <milhead@gmail.com> Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4173 Tested-by: jenkins Reviewed-by: Miller Lowe <miller.lowe@trailtech.net> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Steven Stallion [Thu, 22 Jun 2017 05:14:08 +0000 (22:14 -0700)]
rtos: better sanity checking for uCOS-III
This patch improves the OSRunning check. If the rtos_running check
fails, update_threads will return an error rather than attempt to update
the thread list using bad values.
Change-Id: I8614c325504d3a9ab19aebb6862b1fe445a0c8e7 Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/4166 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Steven Stallion [Wed, 3 May 2017 17:17:45 +0000 (12:17 -0500)]
rtos: style corrections for uCOS-III
This patch corrects a number of style infractions in RTOS support for
uC/OS-III. These were missed during initial review last year prior to
the 0.10.0 release.
Change-Id: Ia2139f6ca381d4087fd8ee989f7a03ac474d7440 Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/4120 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tomas Vanek [Fri, 10 Mar 2017 20:43:46 +0000 (21:43 +0100)]
flash Kinetis: add KL28 device
This device differs a lot from others in KL series.
Unfortunately the System Integration Module, where device
identification resides, moved to a new address so probe now have
to try both addresses of SIM_SDID.
Introduce a new bank creation option: -sim-base to ensure error free probe.
WDOG32 is slightly different from KE1x and on different address.
System Mode Controler changed layout to word aligned.
Tomas Vanek [Mon, 26 Dec 2016 14:20:33 +0000 (15:20 +0100)]
flash Kinetis: implement automatic bank creation based on device probe
Kinetis flash driver services huge number of MCU types. They have
one, two or four flash banks with option of FlexNVM. It would
require ~36 config files just for Kx series, more for KLx, KVx and KE1x.
The change implements alternative approach:
- configuration file creates just one pflash bank (common for all devices)
- when a device is probed, additional pflash or flexnvm banks are created
based on flash layout of the connected MCU
- created banks have names with optional numbering e.g. kx.pflash0 kx.pflash1
kx.flexnvm0 kx.flexnvm1
- the first bank gets renamed if numbering is used
Automatic bank creation is enabled by tcl command 'kinetis create_banks'.
Used solution has a drawback: other banks than pflash0 are not accessible
until pflash0 is probed. Fortunately gdb attach and standard programming
accesses banks in right sequence.
Tomas Vanek [Mon, 26 Dec 2016 09:15:06 +0000 (10:15 +0100)]
flash Kinetis: split kinetis_chip from kinetis_flash_bank
Kinetis flash driver probed and decoded chip repeatedly for each flash
bank. Bank ordering used global bank number so multi-target
configuration was broken.
The change introduces kinetis_probe_chip() which reads SIM SDID
and SIM FCFG registers, decodes Kinetis series and family
and fills struct kinetis_chip. This probe runs once for all banks.
struct kinetis_chip contains pointers to all flash banks embeded
in the MCU. It simplifies iteration over all or specific MCU banks.
kinetis_probe_chip() generates MCU name and some informational messages
are improved.
Tomas Vanek [Fri, 2 Dec 2016 14:47:01 +0000 (15:47 +0100)]
flash Kinetis: add KL8x family, fix erase check
Secure devices KL81Z7 and KL82Z7 have no SERIESID field in ID register
so they have to be decoded in Kx branch (not KLx).
The flash controller in KL8x and also in K8x devices does not implement
FTFx_CMD_BLOCKSTAT command. Fix kinetis_blank_check() to work properly
using FTFx_CMD_SECTSTAT command only.
Introduce a new flag FS_NO_CMD_BLOCKSTAT to avoid use of FTFx_CMD_BLOCKSTAT
on these devices.
Tomas Vanek [Wed, 30 Nov 2016 20:48:59 +0000 (21:48 +0100)]
flash Kinetis: add KE1xZ and KE1xF families
The new Kinetis KE1x families use FTFE flash controller unlike KE0x.
Also SDID coding corresponds to new K, KL and KV families.
That's why KE1x is handled by kinetis driver instead of kinetis_ke
Tomas Vanek [Thu, 14 Jul 2016 18:52:13 +0000 (20:52 +0200)]
flash/nor: at91samd modified to use real erase sector size
Before this change SAMD driver defined "sector" equal to a flash
protection block. Oversize sectors (16kB for the biggest flash size)
made problems for flashing firmware split to two or more parts.
Removed superfluous test of sector protection before erase.
Tomas Vanek [Mon, 26 Dec 2016 21:53:44 +0000 (22:53 +0100)]
flash/nor/at91sam4: remove FWS=6, rename at91samg to atsamg
FWS=6 workaround removed, as this appears to be a copy-paste error
from the SAM3X family. Originally addressed in http://openocd.zylin.com/3837
but not all occurences were removed.
Atmel changed chip naming and removed 91 prefix for atsamg, samd...
Extended and revised version of my original patch submitted by Dmytro
here: http://openocd.zylin.com/#/c/3390
This driver is using pure SPI mode, so the flash base address is not
used except some flash commands (e.g. "flash program") need it to
distinguish the banks.
Example config with all 3 chip selects:
flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0
flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
Example usage:
> flash probe flash0
Found flash device 'win w25q128fv' (ID 0x001840ef)
flash 'ath79' found at 0x00000000
> flash probe flash1
No SPI flash found
> flash probe flash2
No SPI flash found
> flash banks
> flash read_bank flash0 /tmp/test.bin 0x00000000 0x1000
reading 4096 bytes from flash @0x00000000
wrote 4096 bytes to file /tmp/test.bin from flash bank 0 at offset
0x00000000 in 28.688066s (0.139 KiB/s)
Grzegorz Kostka [Tue, 18 Apr 2017 14:12:58 +0000 (16:12 +0200)]
imx_gpio: add mmap based jtag interface for IMX processors
For some targets (like nrf51) sysfs driver is too slow. This
patch implements memory maped driver for IMX processors.
Mostly based on bcm2835gpio. Tested on imx6ul CPU. However, it should
work on any NXP IMX CPU.
Change-Id: Idace4c98181c6e9c64dd158bfa52631204b5c4a7 Signed-off-by: Grzegorz Kostka <kostka.grzegorz@gmail.com>
Reviewed-on: http://openocd.zylin.com/4106 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Salvador Arroyo [Mon, 20 Feb 2017 19:45:37 +0000 (20:45 +0100)]
mips32, use scan32 function for reading impcode/idcode.
There is no need to implement scan code in functions
mips_ejtag_get_idcode/impcode(), use mips_ejtag_drscan_32().
Impcode/idcode saved in ejtag.info.
Reorder the code in the callers of this functions.
Change-Id: Ia829c783a0b24c6a65cade736113fa6f67b0a170 Signed-off-by: Salvador Arroyo <salvador@telecable.es>
Reviewed-on: http://openocd.zylin.com/4003 Tested-by: jenkins Reviewed-by: Peter Mamonov <pmamonov@gmail.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Salvador Arroyo [Mon, 8 May 2017 07:44:50 +0000 (09:44 +0200)]
mips32: add micromips breakpoints support
Breakpoint setting based on length (kind) only.
Added 16bit aligned 32bit software breakpoints
support and same filtering before setting
breakpoint.
Set the required isa bit in hardware breakpoints.
Drop the isa bit in software breakpoints.
Salvador Arroyo [Sun, 7 May 2017 16:39:17 +0000 (18:39 +0200)]
mips32: add micromips isa handling
Read and save configuration registers, up to 4.
Config3 holds the micromips implementation info.
Added isa implementation info to mips32_common.
Added isa filter to avoid common mistakes, but only
if one isa mode is implemented.
When resuming the isa requested is set if more than
one isa mode is implemented.
Salvador Arroyo [Sun, 7 May 2017 09:58:25 +0000 (11:58 +0200)]
mips32, add support for micromips in debug mode
Micromips is 16bit oriented, branch and jumps are
16 bit based. The upper half 16bits of a 32bit instruction
with the major opcode, must go first in the instruction
stream, hence the SWAP16 macro and swap16 array function,
needed if the code is written as 32 bit word in little endian
cores. Endianess info added to ejtag_iinfo. Pointer to
ejtag_info and isa field added to pracc context.
MIPS32 code are renamed to MIPS32_ISA_...
To select the isa, the new code has an additional isa parameter
(1 for micromips, 0 for mips32).
In JR instruction the isa bit must be set to execute
micromips code.
The suffix u is added to the OP codes to avoid signed/unsigned
comparison errors and to make sure the right shift is
performed logically.
The isa in debug mode is updated in the poll function.
Code for miniprograms, in kernel mode, need to be converted.
CFI code only for mips32.
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