Tomas Vanek [Fri, 2 Oct 2015 12:31:30 +0000 (14:31 +0200)]
Kinetis: properly pad flash section writes
kinetis_write() with byte count not divisible by prog_section_chunk_bytes
computed wrong wc and therefore paded section chunk by some
random data instead of 0xff
Change-Id: Ic7c66d8a3ceacda9e611e98b9fbf943b8001774b Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2994 Tested-by: jenkins Reviewed-by: Thomas Schmid <thomas@rfranging.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Thomas Schmid [Wed, 30 Sep 2015 15:40:10 +0000 (09:40 -0600)]
Kinetis: Disable watchdog on Kx devices when programming.
Kx devices with FTFA flash need the watchdog disabled when programming.
I tried to keep overhead as small as possible and re-use registers that
were already inquired (e.g. sim_sdid).
Change-Id: Ibc29a26ec34102d78a6c3920dd16f63e134a8f6f Signed-off-by: Thomas Schmid <thomas@rfranging.com>
Reviewed-on: http://openocd.zylin.com/2986 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The change concerns the "Black" variant of the TI BeagleBone, while the
configuration file is for the original BeagleBone board, which actually
embeds a debug interface on the PCB.
This makes it easier to relocate the install tree of OpenOCD from where
it was originally built (for example, if put onto a different machine),
without having to change scripts or add something to the command line
every time.
Change-Id: Ia5edf0eba166f7a999f267bd6a92402dab9b399e Signed-off-by: Jonathan Larmour <jifl@eCosCentric.com>
Reviewed-on: http://openocd.zylin.com/3004 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
If we work on smp system, the output of step command will depend
on Id of default target.
This patch adds additional information to help find what on which
core is happening.
Example of LOG after this patch.
imx6.cpu.1: target state: halted
^^^^^^^^^^
target halted in ARM state due to breakpoint, current mode: Supervisor
cpsr: 0x60000093 pc: 0x80076c0c
MMU: enabled, D-Cache: enabled, I-Cache: enabled
imx6.cpu.0: target state: halted
^^^^^^^^^^
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x20000193 pc: 0x802ccb6c
MMU: enabled, D-Cache: enabled, I-Cache: enabled
Tomas Vanek [Thu, 1 Oct 2015 17:17:41 +0000 (19:17 +0200)]
cortex_m: dwt_num_comp should be set to zero in cortex_m_dwt_free()
A segmentation fault in cortex_m_endreset_event() is sometimes raised
with very broken target like Kinetis Kx with erased flash and active WDOG.
Debugging revealed that cortex_m->dwt_num_comp is 4 and
dwt_list is NULL at cortex_m:290
Change-Id: I229c59d6da13d816df513d1dbb19968e4b5951e2 Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2989 Reviewed-by: Thomas Schmid <thomas@rfranging.com> Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
daniel-k [Wed, 14 Oct 2015 15:30:57 +0000 (17:30 +0200)]
rtos/mqx: Fix uninitialized parts of symbol table
Memory for the symbol table was allocated by malloc but not initialized other
than with the symbol name. Therefore `address` and `optional` members were
having arbitrary values leading to every symbol being optional most of the
time which messes up RTOS auto-detection. Memory will now be zero-initialized
as in other RTOS implementations.
Andrew Ruder [Mon, 5 Oct 2015 18:52:43 +0000 (13:52 -0500)]
rtos: handle STKALIGN adjustments on cortex m
In the case that the STKALIGN bit is set on Cortex M processors, on
entry to an exception - the processor can store an additional 4 bytes
of padding before regular stacking to achieve 8-byte alignment on
exception entry. In the case that this padding is present, the
processor will set bit (1 << 9) in the stacked xPSR register. Use the
new calculate_process_stack callback to take into account the xPSR
register and use it on the standard Cortex_M3 stacking.
Note: Change #2301 had some misinformation regarding the padding. On
Cortex-M the padding is stored BEFORE stacking so xPSR is always
available at a fixed offset.
Tested on a Cortex-M0+ (Atmel SAMR21) board which has STKALIGN fixed
to a '1' such that this alignment always occurs on non-aligned stacks.
Behavior of xPSR verified via the (bad-sorry) assembly program below by
setting a breakpoint on the SVC_Handler symbol. The first time
SVC_Handler is triggered the stack was 0x20000ff8, the second time
SVC_Handler is triggered the stack was 0x20000ffc. Note that in both
cases the interrupt handler gets 0x20000fd8 for a stack pointer.
GDB exerpt:
Breakpoint 1, 0x000040b6 in Reset_Handler ()
(gdb) hbreak SVC_Handler
Hardware assisted breakpoint 2 at 0x40f8
(gdb) cont
Continuing.
@ first call - 0x2000fff8 -- should already be aligned
@ second call - 0x2000fffc -- should hit the alignment code
.global SVC_Handler
SVC_Handler:
bx lr
Change-Id: Id0940e6bbd6a59adee1378c0e86fe86830f0c8fc Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com> Cc: Paul Fertser <fercerpav@gmail.com> Cc: Andreas Fritiofson <andreas.fritiofson@gmail.com> Cc: Evan Hunter <evanhunter920@gmail.com> Cc: Jon Burgess <jburgess777@gmail.com>
Reviewed-on: http://openocd.zylin.com/3003 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Andrew Ruder [Mon, 5 Oct 2015 18:51:10 +0000 (13:51 -0500)]
rtos: turn stack alignment into a function pointer
Some targets (Cortex M) require more complicated calculations for
turning the stored stack pointer back into a process stack pointer.
For example, the Cortex M stores a bit in the auto-stacked xPSR
indicating that alignment had to be performed and an additional 4
byte padding is present before the exception stacking. This change
only sets up the framework for Cortex-M unstacking and does not
add Cortex-M support.
Note: this also fixes the alignment calculation nearly addressed by
change #2301 entitled rtos/rtos.c: fix stack alignment calculation.
Updated calculation is in rtos_generic_stack_align.
Change-Id: I0f662cad0df81cbe5866219ad0fef980dcb3e44f Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com> Cc: Paul Fertser <fercerpav@gmail.com> Cc: Andreas Fritiofson <andreas.fritiofson@gmail.com> Cc: Evan Hunter <evanhunter920@gmail.com> Cc: Jon Burgess <jburgess777@gmail.com>
Reviewed-on: http://openocd.zylin.com/3002 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
Ivan De Cesaris [Mon, 26 Oct 2015 15:50:34 +0000 (16:50 +0100)]
quark: updating license to GPLv2+
Intel is relicensing our contributions to OpenOCD under GPL
version 2 or any later version. We previously contributed code
under GPL version 2 only. It was not our intention to differ
from the standard OpenOCD license. We're correcting that here.
This also applies retroactively to previous versions of our
contributions to OpenOCD.
Change-Id: I5e831ed95d03d2044d8e5a8375b21c6e52c933d7 Signed-off-by: Ivan De Cesaris <ivan.de.cesaris@intel.com>
Reviewed-on: http://openocd.zylin.com/3044 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Andreas Färber [Sun, 10 May 2015 12:45:32 +0000 (14:45 +0200)]
tcl/target: Add config for XMOS XS1-XAU8A-10's ARM core
The XS1-XAU8A-10 has 8 xCORE cores and one ARM core.
This config represents the ARM Cortex-M3 core, which is apparently
Silicon Labs EFM32 Giant Gecko IP.
Change-Id: I998360f096c759d2e274d96c1ca2e0450ba61146 Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2762 Tested-by: jenkins Reviewed-by: Oleksij Rempel Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
tcl: Support for reading "Device DNA" from Spartan 6 devices.
Most Xilinx FPGA devices contain an embedded, unique device identifier
called the "Device DNA". The identifier is nonvolatile, permanently
programmed into the FPGA, and is unchangeable providing a great serial
/ tracking number.
Debugging was done in https://github.com/timvideos/HDMI2USB/issues/36
Change-Id: Iad03eafb40887f0321a4dc22858a7c3bf37a12b3 Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
Reviewed-on: http://openocd.zylin.com/2960 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Peter A. Bigot [Thu, 13 Aug 2015 14:20:25 +0000 (09:20 -0500)]
nrf51: recognize hwid 0084
Chip markings: N51822 / QFACA1 / 1513AN
Change-Id: Idb7fc723850ea08b60b9f5c97a53f1ae8dfc8eb2 Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Reviewed-on: http://openocd.zylin.com/2936 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tomas Vanek [Tue, 14 Jul 2015 20:10:55 +0000 (22:10 +0200)]
Kinetis: new devices K02, K26, K63, K64, K66, correct K21 and K22 variants
K22FN1M0 and K22FX512 has FTFE flash and old style SDID.
K22FN128, 256 and 512 has FTFA flash and new style SDID
K63 and K64 detects as K61 and K62, see Errata 1N83J e7534
Change-Id: I2aca6f1f18819bb2b2ec4982036510de444ad2ac Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2867 Tested-by: jenkins Reviewed-by: Thomas Schmid <thomas@rfranging.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Patrick Stewart <patstew@gmail.com>
Tomas Vanek [Thu, 24 Sep 2015 08:29:12 +0000 (10:29 +0200)]
Kinetis: give a reasonable default for max_flash_prog_size
max_flash_prog_size euals to pflash_sector_size_bytes for most of devices.
There is no point setting max_flash_prog_size for devices without
FS_PROGRAM_SECTOR capability.
Check for zero sector_size to avoid div by zero exception in case of
device has FlexNVM but the driver does not define nvm_sector_size_bytes
Change-Id: Iaf4e007fb1ec3d24c373350410e4bebe504a4c3e Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2958 Tested-by: jenkins Reviewed-by: Thomas Schmid <thomas@rfranging.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Patrick Stewart <patstew@gmail.com>
Patrick Stewart [Fri, 10 Jul 2015 13:01:35 +0000 (14:01 +0100)]
Kinetis: Add K24 support and tidy up
The K24 uses the KL-style SDID register and has some flashing quirks, so the kinetis driver does not support it properly.
Extend the chip detection routine to support the new SDID format. Add a parameter for the maximum flash size, as the K24 only supports 1k flashing blocks but has 4k sector size. Remove global 'granularity' array, as it's only really needed in one function. Replace 'klxx' with an enum showing which flash commands are actually supported on a given chip.
Signed-off-by: Patrick Stewart <patstew@gmail.com>
Change-Id: Ie244fab564d58c5cfe4fa36a025f0b2674ffad69
Reviewed-on: http://openocd.zylin.com/2864 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Jim Paris [Fri, 11 Sep 2015 17:00:54 +0000 (13:00 -0400)]
stlink_usb: fix typo
Change-Id: I3cf5ced568319878b8bf40743e4c07718f630c68 Signed-off-by: Jim Paris <jim@jtan.com>
Reviewed-on: http://openocd.zylin.com/2953 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Andreas Färber [Thu, 23 Apr 2015 12:06:46 +0000 (14:06 +0200)]
tcl/board: Add Parallella-I board config
Tested with Porcupine-1 JTAG adapter board and Digilent JTAG-HS3 interface;
reset does not yet work, pending nSRST configuration of the interface used.
Change-Id: I0d0679e098d93ffbd1539004cdb900e2a8ae4a25 Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2730 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Philipp Wagner [Tue, 23 Jun 2015 14:49:22 +0000 (16:49 +0200)]
tcl_server: Support line buffers up to 4M (v3)
Currently, the maximum size of a command sent to the TCL server is
4k. This patch increases this limit up to 4M.
Reasoning:
To get high-speed JTAG data transfers, I'm using a very long shift
register. This reduces the overhead of the state changes, as well as the
latency due to the common USB adapter transfers considerably. In order
to submit those long DRSCAN commands to OpenOCD over the TCL/TCL
interface, long TCL command lines are required. This is enabled by this
patch.
v3:
Address review comments. Drop line instead of connection when realloc()
fails.
Changes in v2 of this patch:
The line buffer is allocated dynamically to avoid an OpenOCD memory
overhead if the large buffers are not used. The buffer starts at 4K and
increases exponentially up to 1M, and then linearly in 1M increments up
to 4M.
Change-Id: Iecaef6a56ed5e18e9de4d912a514031ea78fa3bd Signed-off-by: Philipp Wagner <philipp.wagner@tum.de>
Reviewed-on: http://openocd.zylin.com/2837 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Alamy Liu [Thu, 6 Aug 2015 21:45:19 +0000 (14:45 -0700)]
flash/nor/jtagspi: 'retval' may be used uninitialized
Problem
As my compiler has "warnings being treated as errors" on, it shows the
error message:
error: 'retval' may be used uninitialized in this function
Investigation
Nothing wrong with the logic, 'retval' would have a value before returning.
Just wanna get rid of the compiling "warning as error" message.
Solution
Provide a reasonable default value
Change-Id: I712c15f82819c6c48bee9dceca8de4b18aeb29b0 Signed-off-by: Alamy Liu <alamy.liu@gmail.com>
Reviewed-on: http://openocd.zylin.com/2905 Tested-by: jenkins Reviewed-by: Robert Jordens <jordens@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Paul Fertser [Thu, 30 Jul 2015 08:55:43 +0000 (11:55 +0300)]
svf: flush the queue before reallocing memory
During reallocation a new memory region might be allocated and the old
one freed. If jtag queue is holding a pointer to the old memory, it will
segfault during the execution. Avoid this by flushing the queue before a
reallocation attempt is made.
This should fix ticket #102.
Change-Id: I737fc3f1ebf6d76413a475beb8bf20184fe0233f Reported-by: Alex Forencich <aforencich@users.sf.net> Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2899 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Andrey Yurovsky [Wed, 10 Jun 2015 16:53:27 +0000 (09:53 -0700)]
at91samd: add chip IDs for SAMC20 and SAMC21 families
Add the chip IDs corresponding to the new 5V "SAMC" parts which are
otherwise identical to the SAMD and should work with this driver. Also
add the configurations for their Xplained Pro boards.
Paul Fertser [Fri, 26 Jun 2015 06:54:07 +0000 (09:54 +0300)]
sim3x: fix build failure with clang 3.6
This fixes a warning as reported by the current clang version:
../../../../src/flash/nor/sim3x.c:867:20: error: address of array
'sim3x_info->device_package' will always evaluate to 'true' .
Change-Id: Ie160cbe6df8f491e9beff38d47e2f13575529bf9 Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2838 Tested-by: jenkins Reviewed-by: Oleksij Rempel Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Robert Jordens [Thu, 2 Jul 2015 05:29:34 +0000 (23:29 -0600)]
pipistrello: ftdi-jtag/spartan6/jtagspi board
The Pipistrello is a low cost FPGA board with a Xilinx
Spartan6 LX45, a SPI flash and onboard FTDI JTAG.
This board is a good example use case for the jtagspi
flash driver talking through a proxy bitstream.
Change-Id: I04a80610ff825c36ebcb67b879507028eed141ad Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/2846 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Robert Jordens [Wed, 1 Jul 2015 09:18:46 +0000 (03:18 -0600)]
flash/nor/jtagspi: add JTAGSPI driver
Many FPGA board speak JTAG and have a SPI flash for their bitstream
attached to them. The SPI flash is programmed by first uploading a
proxy bitstream to the FPGA that connects the JTAG interface to the
SPI interface if the IR contains a certain USER instruction. Then the
SPI flash can be erase, written, read directly through the JTAG DR.
The JTAG and SPI signaling is compatible. Such a proxy bitstream only
needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the
chip select when the IR contains the special instruction and the JTAG
state machine is in the DR-SHIFT state.
Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Robert Jordens [Wed, 1 Jul 2015 08:55:49 +0000 (02:55 -0600)]
flash/nor/tcl: add read_bank and verify_bank
The only read access to flash chips so is through the target's
memory. Flashes like jtagspi do not expose a memory mapped interface
to the flash. These commands use the flash_driver_read() driver API
directly.
Change-Id: I40b910de650114a3f676507f9f059a234377d862 Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/2842 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Robert Jordens [Fri, 3 Jul 2015 05:15:53 +0000 (23:15 -0600)]
cpld/virtex2: allow JSTART to be disabled
This adds an option to disable the use of the JSTART instruction
when loading bitstreams to xilinx fpgas. JSTART apparently prevents
configuration if the startup clock is not set to the jtag clock in
the bitstream.
xc3sprog is omitting JSTART for all devices. Problems with loading a bitstream
that does not have StartupClk:JTAGClk are described here:
http://www.xilinx.com/support/answers/56151.html
Change-Id: I8137c0bae05a8c3c6f8e2611869f70a770d1651d Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/2860 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Robert Jordens [Tue, 30 Jun 2015 23:16:08 +0000 (17:16 -0600)]
target/testee: manage target->state
The testee target is usefull for certain non-cpu pass-through
situations, for example in the case of a spi flash mapped to the DR of
a JTAG tap, as is the case for most FPGAs with SPI flashs behind them.
We just manage the RUNNING/RESET/HALTED state in the testee driver to
support it being halted which is a requirement for flash banks.
Change-Id: I1b4d52c58a1f6bd753e126bfde74dcc5164d7b69 Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/2840 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Kyle Manna [Sun, 17 May 2015 18:11:26 +0000 (11:11 -0700)]
jlink: Add on-board nRF51-DK USB VID and PID
* Add USB VID and PID for the J-Link interface running on the Nordic
Semiconductor nRF51-DK. Also tested with debug out port to debug
external boards.
* Elimiantes need for `-c "jlink pid 0x1015"` on the openocd cmd line.
Change-Id: Ib23acb72b9f5183b76fc7dc22b556982869ae830 Signed-off-by: Kyle Manna <kyle@kylemanna.com>
Reviewed-on: http://openocd.zylin.com/2775 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Kyle Manna [Sun, 17 May 2015 18:11:15 +0000 (11:11 -0700)]
udev: Add J-Link on-board nRF51-DK
* Add USB VID and PID for the J-Link interface running on the Nordic
Semiconductor nRF51-DK. Also tested with debug out port to debug
external boards.
* Fixes permissions problems.
Change-Id: I01ffc3150fa2af92d399b50e0195dc255a40ec42 Signed-off-by: Kyle Manna <kyle@kylemanna.com>
Reviewed-on: http://openocd.zylin.com/2774 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Peter A. Bigot [Tue, 10 Mar 2015 13:44:28 +0000 (08:44 -0500)]
nrf51: refine and extend known devices table
The notation Gx0 in the nRF51 Series Compatibility Matrix indicates that
the specified HWID is valid only for build code 0 of each chip, and for
subsequent builds the HWID will be different. Replace the Gx0 notation
with G0 throughout, and add the missing HWID for nRF51422 QFAC A1
(present on the newer nRF51 developer boards).
projects / openocd / log