Zachary T Welch [Sat, 5 Dec 2009 00:07:47 +0000 (16:07 -0800)]
split flash.h into into flash/nor/*.h
Move the bulk of the flash.h file into flash/nor/core.h, leaving an
empty husk that will be removed in the next patch.
The NOR driver structure is an implementation detail, so move it into
its own private header file <flash/nor/driver.h> along with helper
declaration for finding them by name.
Zachary T Welch [Fri, 4 Dec 2009 12:01:45 +0000 (04:01 -0800)]
move more nor flash implementation details
Splits the exec mode commands out of flash.c into the flash/nor/ files.
The routines used by these high-level commands are moved into nor/core.c,
with their internal declarations placed in nor/imp.h.
David Brownell [Sat, 5 Dec 2009 00:51:48 +0000 (16:51 -0800)]
ARM: semihosting entry cleanup
Clean up arm_semihosting() entry a bit, comment some issues and just
which SVC opcodes are getting intercepted. Microcontroller profile
cores will need a new entry, since they use BKPT instead (and don't
have either SVC mode or an SPSR register).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Zachary T Welch [Fri, 4 Dec 2009 00:47:49 +0000 (16:47 -0800)]
add flash/nor/{tcl.c,imp.h} from flash/flash.c
Moves the top-level 'flash' command handlers into flash/nor/tcl.c,
with flash/nor/imp.h providing an internal implementation header
to share non-public API components.
Zachary T Welch [Fri, 4 Dec 2009 00:25:51 +0000 (16:25 -0800)]
separate Jim from jtag/core.c
After previous efforts, only one Jim routine remained in jtag/core.c,
and moving it to jtag/tcl.c painlessly finishes separating these layers.
The headers need separating, but the implementation is clean.
Zachary T Welch [Fri, 4 Dec 2009 01:38:24 +0000 (17:38 -0800)]
check top-level command registrations
When calling module_register_commands, the return value needs to be
checked for failures. Instead of duplicating code, use an array of
function pointers to the identical registration functions to iterate
over during startup.
Nicolas Pitre [Thu, 3 Dec 2009 22:27:13 +0000 (17:27 -0500)]
basic ARM semihosting support
Semihosting enables code running on an ARM target to use the
I/O facilities on the host computer. The target application must
be linked against a library that forwards operation requests by
using the SVC instruction that is trapped at the Supervisor Call
vector by the debugger. The "hosted" library version provided
with CodeSourcery's Sourcery G++ Lite for ARM EABI is one example.
This is currently available for ARM9 processors, but any ARM
variant should be able to support this with little additional work.
Tested using binaries compiled with Sourcery G++ Lite 2009q1-161
and ARM RVCT 3.0.
Dean Glazeski [Mon, 16 Nov 2009 19:40:46 +0000 (13:40 -0600)]
Make ARM NAND I/O operations aware of last op
Updates the ARM NAND I/O code to look at and update the op
field of arm_nand_data to reflect the last operation performed.
It uses this field to copy the correct code to the target in the
case where the struct is used for reads and writes.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Dean Glazeski [Mon, 16 Nov 2009 19:34:24 +0000 (13:34 -0600)]
ARM NAND I/O interface update
Modify the arm_nand_data struct to better support both read and
write operations while using the same struct. An additional
field was added, and initialized, to record the last operation
so that the correct code can be loaded to the working area.
David Brownell [Fri, 4 Dec 2009 00:08:04 +0000 (16:08 -0800)]
ARM DPM: share debug reason logic
No point in both ARM11 and Cortex-A8 having private copies
of the logic sorting out e.g. DBG_REASON_WATCHPOINT.
Add and use a shared routine for this ... there's actually
a bunch more debug entry logic that could be shared, this
is just a start on that. Note that this routine fixes a
bug observed in the ARM11 code, where some abort mode quirks
were displayed as being an unknown debug reason; and also
silences needless ARM11 chatter.
Likewise with private copies of DSCR ... add one to the DPM
struct. Save it as part of setting DBG_REASON_* so later
patches can switch over to using that copy.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Fri, 4 Dec 2009 00:08:04 +0000 (16:08 -0800)]
ARM11: use shared DSCR bit names
For the bits now defined in "arm_dpm.h", switch to the
shared DSCR_* symbol and remove the ARM11_DSCR_* version.
Define DSCR_INT_DIS and use it instead of the ARM11_DSCR_*
sibling symbol. (Note: for both ARM11 and Cortex-A8, this
should arguably be enabled by default when single stepping.)
Remove some other unused declarations in "arm11.h".
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Fri, 4 Dec 2009 00:08:04 +0000 (16:08 -0800)]
ARM DPM: make DSCR bit defs sharable
Move the symbols for these bits from "armv7a.h" to "arm_dpm.h",
where they can be seen and used not just by Cortex-A but also
by the ARM11 (armv6) code.
Change them from bit numbers to bit masks ... this matches the
usage in ARM11 code, and also makes it easier to read.
Rename DSCR_EXT_INT_EN as DSCR_ITR_EN to match the docs; it's
enabling ITR functionality, not external interrupts, so this
changes the name to be less misleading. (There *IS* a bit
affecting interrupts, and this isn't it.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Thu, 3 Dec 2009 22:44:03 +0000 (14:44 -0800)]
fix another init regression
This makes Beagle work again, instead of losing horribly because
the JTAG event handlers are no longer able to e.g. "runtest". I
get the previous quirky behavior ... comes up OK but "reset halt"
somewhat mysteriously makes it all better. (Instead of nothing
being able to work at all...) However, I'm still seeing:
The 'init' command must be used before 'init'.
That seems to come from invoking "jtag init", sometime after it
gets mapped to "ocd_jtag init", according to debug message traces.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Zachary T Welch [Thu, 3 Dec 2009 13:23:16 +0000 (05:23 -0800)]
fix double 'init' regression
To prevent regression in the behavior of 'init', we allow it to run in
any mode. If provided with -c init and with -c noinit, then the second
init at startup caused a spurious mode failure. Let 'init' handle it.
Zachary T Welch [Thu, 3 Dec 2009 13:13:45 +0000 (05:13 -0800)]
fix regressions with GDB port numbers
Use a separate variable for iterating GDB service port numbers than
the one set by the user. Restores the behavior of returning the
original port number and only incrementing the port used on success.
Zachary T Welch [Thu, 3 Dec 2009 11:46:15 +0000 (03:46 -0800)]
change #include "../hello.h" to "hello.h"
Before we can -I the top-level src/ directory alone, references to
"hello.h" must be updated. This is an internal header, so it does
not need angle brackets.
David Brownell [Thu, 3 Dec 2009 06:57:08 +0000 (22:57 -0800)]
ARM11: don't expose DSCR
Remove the remaining extra copy of DSCR, and the register cache
of which it was a part. That cache wasn't a very safe, or even
necessary, idea; it was essentialy letting debugger-private state
be manipulated by Tcl code that couldn't know how to do it right.
This makes the "reg" output of an ARM11 resemble what most other
ARM cores produce ... forward motion in the "make ARM11 work like
the rest of the ARM cores" Jihad!
David Brownell [Thu, 3 Dec 2009 06:57:08 +0000 (22:57 -0800)]
ARM11: store a clean copy of DSCR
Just store a clean copy of DSCR in the per-CPU struct, so we
trivially pass a pointer to a recent copy. This replaces the
previous "last_dscr" and cleans up most of the related calling
conventions ... but it doesn't remove the other DSCR copy.
David Brownell [Thu, 3 Dec 2009 06:57:07 +0000 (22:57 -0800)]
ARM11: don't expose WDTR
Don't expose the WDTR register through the register cache any
more. If anyone wants Tcl scripts to be able to use DCC based
communication with app code in the target, this wouldn't do it.
Bugfix: don't trust the Tcl-accessible version of DSCR to
flag whether WDTR needs to be restored when resuming.
David Brownell [Thu, 3 Dec 2009 06:57:07 +0000 (22:57 -0800)]
ARM11: don't expose RDTR
Don't expose the RDTR register through the register cache any
more. If anyone wants Tcl scripts to be able to use DCC based
communication with app code in the target, this wouldn't do it.
Bugfix: don't trust the Tcl-accessible version of DSCR to
flag whether RDTR needs to be restored when resuming.