Zachary T Welch [Thu, 22 Oct 2009 14:44:54 +0000 (07:44 -0700)]
Add macro for parsing numeric command arguments.
This helper eliminates significant amount of redundant code in command
handler functions throughout the system. It wraps the lower-level
parse_* macros to implement a policy for reporting parse errors to the
active command context (cmd_ctx). If errors do occur, this macro causes
the calling function to abort with the proper return code.
David Brownell [Thu, 5 Nov 2009 19:31:32 +0000 (11:31 -0800)]
User's Guide: TAP setup tweakage
Highlight that the "-expected-id" probably comes from vendor
documentation, and that it *should* be used where possible.
Don't use ircapture/irmask in examples, to help discourage
use of those params when they're not required. Explain a
bit better about why/when those params get used.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Thu, 5 Nov 2009 09:47:44 +0000 (01:47 -0800)]
watchpoint_add() cleanup
Fail watchpoint_add() if it's the same address but the
parameters are different ... don't just assume having
the same address means the same watchpoint! (Note that
overlapping watchpoints aren't detected...)
Handle unrecognized return codes more sanely; don't exit()!
And describe command params right.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Thu, 5 Nov 2009 09:04:08 +0000 (01:04 -0800)]
Cortex-M3: expose most DWT registers
Expose most DWT registers via Tcl; there are a few more, but
those are mostly for profiling along with the ITM. Having
this set available enables operations which aren't possible
with just the standard watchpoint operations.
The cycle counter may be interesting. Turn it on after reset
by setting the LSB of the dwt_ctrl register, and it counts
CPU clocks. You can program the comparator 0 watchpoint to
trigger on a given cycle count, rather than a data address.
Likewise, comparator 1 may be able to match data values given
address matches from one or two other comparators. (Not all
hardware supports this capability though; try it. That is
something the standard watchpoint methods should eventually
handle, for the single address case.)
Minor cleanup: remove needless functional indirection for
exposing the v7m architctural registers.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Thu, 5 Nov 2009 09:03:54 +0000 (01:03 -0800)]
Cortex-M3: minor cleanup
There's no reason to read which interrupts are enabled from
the NVIC; that state isn't used. Plus, it's highly dynamic
since firmware can change it at any time; remove the support
for those state records.
Remove duplicate definition of DWT_CTRL address; shrink a line.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Thu, 5 Nov 2009 09:03:17 +0000 (01:03 -0800)]
Cortex-M3: DWT cleanup/fixes
Fix the watchpoint error checks, and do them in add(), not later
in set() when it's mostly too late. Support the full range of
watchpoint sizes (1 to 32K bytes each), and check alignments.
Minor cleanup of DWT access: shrink lines, use "+" for address
calculations, comment a few issues. Add debug message reporting
DWT capabilities, matching the message for FBP, and some minor
code and spec review comments.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Øyvind Harboe [Tue, 27 Oct 2009 13:02:16 +0000 (14:02 +0100)]
target: add target->type->has_mmu fn.
improve default target->read/write_phys_memory, produce
more sensible error messages if the mmu interface
functions have not been implemented yet vs. will
not be implemented(e.g. cortex m3).
Øyvind Harboe [Sat, 31 Oct 2009 12:57:18 +0000 (13:57 +0100)]
target: remove unused interface fn that clutters code
The quit entry point was not being invoked. Just a source
of confusion at this point. XScale ran 100x reset upon
quit, but that code made no sense, wasn't commented
and never invoke.
David Brownell [Thu, 5 Nov 2009 05:11:44 +0000 (21:11 -0800)]
PXA255: support Intel "Lubbock" platform
Config for Intel's "Lubbock" PXA255 development board. Even more
so than the PXA255 itself, this is obsolete. AFAIK this was the
first generally available development platform for PXA255. Intel
stopped providing these after other devel boards became available.
One interesting thing about this board from the OpenOCD perspective
is probably its flash configuration. Each bank is 32 bits wide,
built from two 16-bit StrataFlash chips wired in parallel. This
doubles throughput ... it reads/writes 32 bits in the time a single
chip takes to write just 16 bits.
This conf mostly works, given XScale bugfixes, but has some issues
(notably: no access to the on-board SDRAM) flagged by FIXMEs.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Thu, 5 Nov 2009 01:49:06 +0000 (17:49 -0800)]
Release docs: fix notes
We currently do something unusual: version codes in config.in get
updated after the release, which means that "git describe" won't
match up to development version labels. Comment that trouble spot.
We can fix this by switching away from the major/minor/micro type
release numbering, as various other projects have done. The major
numbers basically don't tend to change, and doing a good job with
micro versions is so annoying that they rarely change either.
David Brownell [Wed, 4 Nov 2009 23:38:06 +0000 (15:38 -0800)]
Tweak release docs
Contrast releases to git snapshot tarballs. Mention that
releases have some quality-improvement focus, with special
non-"dev" version IDs. Explain more about version IDs,
using "openocd -v" to see them, etc;
Make release milestone info be less specific about timing,
and presume we have both a merge window and an RC stage.
Rework the release process information to match reality a
bit more closely. Reference the version.sh script (in one
place the wrong script was referenced). Bugfix branches
get special treatment, while non-bugfix releases are more
or less what *defines* being the mainline branch.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Øyvind Harboe [Mon, 2 Nov 2009 10:10:09 +0000 (11:10 +0100)]
target: require working area for physical/virtual addresses to be specified
Fixed bug: if virtual address for working memory was not specified
and MMU was enabled, then address 0 would be used.
Require working address to be specified for both MMU enabled
and disabled case.
For some completely inexplicable reason this fixes the regression
in svn 2646 for flash write in arm926ejs target. The logs showed
that MMU was disabled in the case below:
David Brownell [Mon, 2 Nov 2009 01:54:47 +0000 (17:54 -0800)]
User's Guide: more init info, autoprobing, etc
Mention the autoprobing as a tool that may be useful when
figuring out how to set up; and add a section showing how
to use that mechanism (with an example).
Strengthen the differences between config and run stage
descriptions; add a section for the latter.
Mention Dragonite.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Freddie Chopin [Thu, 29 Oct 2009 18:23:05 +0000 (19:23 +0100)]
target.cfg: use $_TARGETNAME for flash
This gets rid of runtime warnings from the use of numbers.
STM32 and LPC2103 were tested. Other LPC updates are the
same, and so are safe. The CFI updates match other tested
changes now in the tree.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Sat, 31 Oct 2009 03:21:31 +0000 (20:21 -0700)]
NEWS: more info
There were a few more changes worth mentioning, including support
for more JTAG adapters, boundary scan improvements, another NAND
driver, and the Win64 stuff.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Thu, 29 Oct 2009 19:42:41 +0000 (12:42 -0700)]
XSVF: bugfix handling state paths
Implement XSVF support for detailed state path transitions,
by collecting sequences of XSTATE transitions into paths
and then calling pathmove().
It seems that the Xilinx tools want to force state-by-state
transitions instead of relying on the standardized SVF paths.
Like maybe there are XSVF tools not implementing SVF paths,
which are all that we support using svf_statemove().
So from IRPAUSE, instead of just issuing "XSTATE DRPAUSE"
they will issue XSTATES for each intermediate state: first
IREXIT2, then IRUPDATE, DRSELECT, DRCAPTURE, DREXIT1, and
finally DRPAUSE. This works now.
Handling of paths that go *through* reset is a trifle dodgey,
but it should be safe.
Tested-by: Wookey <wookey@wookware.org> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Wed, 28 Oct 2009 17:53:11 +0000 (10:53 -0700)]
Cortex-M3: remove exports and forward decls
Unneeded exports cause confusion about the module interfaces.
Make most functions static, and fix some line-too-long issues.
Delete some now-obviously-unused code.
The forward decls are just code clutter; move their references
later, after the normal declarations. (Or vice versa.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Wed, 28 Oct 2009 17:42:23 +0000 (10:42 -0700)]
ARM926: remove exports and forward decls
Unneeded exports cause confusion about the module interfaces.
Only the Feroceon code builds on this, so only routines it
reuses should be public.. Make most remaining functions
static, and fix some of the line-too-long issues.
The forward decls are just code clutter; move their references
later, after the normal declarations. Turns out we don't need
even one forward declaration in this file.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Franck HÉRÉSON [Wed, 28 Oct 2009 17:24:55 +0000 (10:24 -0700)]
bugfix: stack corruption loading IHex images
The Hex parser uses a fixed number of sections. When the
number of sections in the file is greater than that, the
stack get corrupted and a CHECKSUM ERROR is detected
which is very confusing.
This checks the number of sections read, and increases
IMAGE_MAX_SECTIONS so it works on my file.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Zachary T Welch [Wed, 21 Oct 2009 00:11:33 +0000 (17:11 -0700)]
Rewrite release script to use GIT.
Update documentation to reflect GIT methodology. Rewrite release.sh
script to use appropriate process. With this update, tools/release.sh
can be used for producing private release tags on local branches.
The documentation still needs work, but their use for v0.3.x should
help rectify the deficiences.
Zachary T Welch [Sat, 24 Oct 2009 10:05:41 +0000 (03:05 -0700)]
Improve .gitignore rules.
A '.*' rule prevents the 'git submodule add' from correctly adding the
first submodule, because it creates the .gitmodule file. This file will
not be added (without -f) result in incomplete submodule commits.
The new rules mask the specific files present in my own build tree, but
additional rules may be needed to hide other types of temporary files.
Nicolas Pitre [Tue, 27 Oct 2009 05:14:34 +0000 (01:14 -0400)]
ARM: fix Thumb mode handling when single-stepping register based branch insns
Currently, OpenOCD is always caching the PC value without the T bit.
This means that assignment to the PC register must clear that bit and set
the processor state to Thumb when it is set. And when the PC register
value is transferred to another register or stored into memory then
the T bit must be restored.
Discussion: It is arguable if OpenOCd should have preserved the original
PC value which would have greatly simplified this code. The processor
state could then be obtained simply by getting at bit 0 of the PC. This
however would require special handling elsewhere instead since the T bit
is not always relevant (like when PC is used with ALU insns or as an index
with some addressing modes). It is unclear which way would be simpler in
the end.
Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Nicolas Pitre [Tue, 27 Oct 2009 05:14:33 +0000 (01:14 -0400)]
ARM: allow proper single stepping of Thumb BL and BLX instructions
Whenever an unconditional branch with the H bits set to 0b10 is met, the
offset must be combined with the offset from the following opcode and not
ignored like it is now.
A comment in evaluate_b_bl_blx_thumb() suggests that the Thumb2 decoder
would be a simpler solution. That might be true when single-stepping of
Thumb2 code is implemented. But for now this appears to be the simplest
solution to fix Thumb1 support.
Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Nicolas Pitre [Tue, 27 Oct 2009 05:14:32 +0000 (01:14 -0400)]
ARM: call thumb_pass_branch_condition() only for actual branch opcodes
Calling it first with every opcodes and then testing if the opcode
was indeed a branch instruction is wasteful and rather strange.
If ever thumb_pass_branch_condition() has side effects (say, like
printing a debugging traces) then the result would be garbage for most
Thumb instructions which have no condition code.
While at it, let's make the nearby code more readable by reducing some of
the redundant brace noise and reworking the error handling construct.
Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Tue, 27 Oct 2009 05:53:18 +0000 (22:53 -0700)]
omap3530: target reset/init improvements
Now I can issue "reset halt" and have everything act smoothly;
the vector_catch hardware is obviously not kicking in, but the
rest of the reset sequence acts sanely.
- TAP "setup" event enables the DAP, not omap3_dbginit
(resolving a chicken/egg bug I noted a while back)
- Remove stuff from omap3_dbginit which should never be
used in event handlers
- Cope better with slow clocking during reset
Also, stop hard-wiring the target name: use the input params in
the standard way, and set up $_TARGETNAME as an output param.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Mon, 26 Oct 2009 23:02:45 +0000 (16:02 -0700)]
ARM ADIv5: "dap info" gets more readable
Make the "dap info" output more comprehensible:
- Don't show CIDs unless they're incorrect (only four bits matter)
- For CoreSight parts, interpret the part type
- Interpret the part number
- Show all five PID bytes together
- Other minor cleanups
Also some whitespace fixes, and shrink a few overlong source lines.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Wookey [Mon, 26 Oct 2009 17:06:05 +0000 (17:06 +0000)]
balloon3 board base config
This is the very basic board config for the balloon3 board cpu JTAG
channel.
The rest of the config comprises another 14 .cfg files which I suspect
openocd doesn't really want all of. I'm still not sure how to deal
with this. I'll post another mail/patch to discuss.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Mon, 26 Oct 2009 07:36:03 +0000 (00:36 -0700)]
JTAG: simple autoprobing
This patch adds basic autoprobing support for the JTAG scan chains
which cooperate. To use, you can invoke OpenOCD with just:
- interface spec: "-f interface/...cfg"
- possibly with "-c 'reset_config ...'" for SRST/TRST
- possibly with "-c 'jtag_khz ...'" for the JTAG clock
Then set up config files matching the reported TAPs. It doesn't
declare targets ... just TAPs. So facilities above the JTAG and
SVF/XSVF levels won't be available without a real config; this is
almost purely a way to generate diagnostics.
Autoprobe was successful with most boards I tested, except ones
incorporating C55x DSPs (which don't cooperate with this scheme
for IR length autodetection). Here's what one multi-TAP chip
reported, with the "Warn:" prefixes removed:
clock speed 500 kHz
There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
AUTO auto0.tap - use "... -irlen 4"
AUTO auto1.tap - use "... -irlen 4"
AUTO auto2.tap - use "... -irlen 6"
no gdb ports allocated as no target has been specified
The patch tweaks IR setup a bit, so we can represent TAPs with
undeclared IR length.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Sun, 25 Oct 2009 20:06:47 +0000 (13:06 -0700)]
xscale: always reload handler after reset
Remove needless debug handler state.
- "handler_installed" became wrong as soon as the second TRST+SRST
reset was issued ... so the handler was never reloaded after the
reset removed it from the mini-icache.
This fixes the bug where subsequent resets fail on PXA255 (if the
first one even worked, which is uncommon). Other XScale chips
would have problems too; PXA270 seems to have, IXP425 maybe not.
- "handler_running" was never tested; it's pointless.
Plus a related bugfix: invalidate OpenOCD's ARM register cache on reset.
It was no more valid than the XScale's mini-icache. (Though ... such
invalidations might be better done in "SRST asserted" callbacks.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Fri, 23 Oct 2009 19:28:03 +0000 (12:28 -0700)]
arm9tdmi vector_catch: reserved means "don't use"
Bit 5 shouldn't be used. Remove all support for modifying it.
Matches the exception vector table, of course ... more than one
bootloader uses that non-vector to help distinguish valid boot
images from random garbage in flash.
David Brownell [Fri, 23 Oct 2009 08:02:22 +0000 (01:02 -0700)]
jtag: clean up TAP state name handling
Some cosmetic cleanup, and switch to a single table mapping
between state names and symbols (vs two routines which only
share that state with difficulty).
Get rid of TAP_NUM_STATES, and some related knowledge about
how TAP numbers are assigned. Later on, this will help us
get rid of more such hardwired knowlege.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Fri, 23 Oct 2009 08:00:32 +0000 (01:00 -0700)]
SVF: clean up, mostly for TAP state name handling
- Use the name mappings all the other code uses:
+ name-to-state ... needed to add one special case
+ state-to-name
- Improve various diagnostics:
+ don't complain about a "valid" state when the issue
is actually that it must be "stable"
+ say which command was affected
- Misc:
+ make more private data and code be static
+ use public DIM() not private dimof()
+ shorten the affected lines
Re the mappings, this means we're more generous in inputs we
accept, since case won't matter. Also our output diagnostics
will be a smidgeon more informative, saying "RUN/IDLE" not
just "IDLE" (emphasizing that there can be side effects).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Nicolas Pitre [Fri, 23 Oct 2009 03:23:44 +0000 (23:23 -0400)]
Ferocion: fix corruption of r0 when resuming Thumb mode
The wrong variable (pc instead of r0) was used. Furthermore, someone
did cover this error by stupidly silencing the compiler warning that
occurred before a dummy void reference to r0 was added to the code.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Thu, 22 Oct 2009 19:01:27 +0000 (12:01 -0700)]
ETM: rename registers, doc tweaks
The register names are perversely not documented as zero-indexed,
so rename them to match that convention. Also switch to lowercase
suffixes and infix numbering, matching ETB and EmbeddedICE usage.
Update docs to be a bit more accurate, especially regarding what
the "trigger" event can cause; and to split the issues into a few
more paragraphs, for clarity.
Make "configure" helptext point out that "oocd_trace" is prototype
hardware, not anything "real".
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
projects / openocd / log