Jan Dakinevich [Mon, 27 Feb 2012 20:51:12 +0000 (00:51 +0400)]
jtag: basic support for P&E Micro OSBDM (aka OSJTAG) adapter
This driver provides support for the P&E Micro OSBDM adapter (sometimes
named as OSJTAG), mounted on the Freescale TWRK60N512 bord. Thus, it
provides a quick start when working with this board. The driver doesn't
use BDM commands, but work with OSBDM adapter using only JTAG commands.
Change-Id: Ibc3779538e666e07651d3136431e5d44344f3b07 Signed-off-by: Jan Dakinevich <jan.dakinevich@gmail.com>
Reviewed-on: http://openocd.zylin.com/492 Tested-by: jenkins Reviewed-by: Tomas Frydrych <tf+openocd@r-finger.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Atmel introduced 7 new Cortex-M3 processors on 2012-02-28
SAM3X4C - 256KB flash
SAM3X4E - 256KB flash
SAM3X8C - 512KB flash
SAM3X8E - 512KB flash
SAM3X8H (Only on dev-kit - not in production...) - 512KB flash
SAM3A4C - 256KB flash
SAM3A8C - 256KB flash
The SAM3X/A processors still suffer from the "6 waitstates needed
to program device" errata.
The CIDR address for the SAM3X/A processors are different from the
other SAM3 processors. Unfortunately, the chip identification register
is not at a constant address across all of the SAM3 series'. As a
consequence, a simple heuristic is used to find where it's
at... If the contents at the first address is zero, then we know
that the second address is where the chip id register is.
We can deduce this because for those SAM's that have the chip id @ 0x400e0940,
the first address, 0x400e0740, is located in the memory map of the Power
Management Controller (PMC). Furthermore, the address is not used by the PMC.
So when read, the memory controller returns zero.
Another interesting change is the flash bank address for flash bank 1.
It is not fixed at 0x00100000 like the Sam3U. Bank 1 of the at91sam3a/x
series starts at 0x00080000 + half the total flash size. Thus for the 256KB
devices Bank 1 is located at 0x000A0000, and for the 512KB devices Bank 1 is
located at 0x000C0000.
The configuration files for the SAM3X/A processors will follow
Øyvind Harboe [Mon, 5 Mar 2012 20:23:20 +0000 (21:23 +0100)]
flash: retire unused eCos flash driver
even the AT91EB40a's flash is covered by CFI and nobody ever submitted
any other drivers based on eCos code. It's just possible that this
idea was missing documentation and "marketing", but it's in git if
somebody wants to resurrect it.
Attila Kinali [Tue, 28 Feb 2012 11:39:41 +0000 (12:39 +0100)]
SAM3: Remove unused reference to SUPC registers
The SUPC (Supply Controller) registers are on different base addresses on different
SAM3 chips:
SAM3U: 0x400e1210
SAM3N: 0x400e1410
SAM3S: 0x400e1410
This creates a problem with the sam3_reg_list array which is const, but would need
to be changed at runtime to account for this variability. As this register is not
used anywhere, it's simplest to just remove it.
Change-Id: I987eb371648d826aa6d5e9de18d38c7bb66d6fca Signed-off-by: Attila Kinali <attila@kinali.ch>
Reviewed-on: http://openocd.zylin.com/495 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This patch moves the bulk of the stlink read/write code into the
stlink_usb_xfer set of functions and implements stlink_usb_recv
in terms of the generic stlink_usb_xfer
stlink_usb_xfer will be needed to implement stlink_usb_send
without code duplication
stlink_usb_xfer:
-sends the stlink command
-performs a read or write (as requested)
-checks the status (v1 only)
Attila Kinali [Fri, 24 Feb 2012 10:18:12 +0000 (11:18 +0100)]
Fix assert to check flash programming offset
The assert introduced in 00c864835149a96b431fc8f31dd89542d88fd383 checks
whether the programming offset equals to page_size of the flash, while it
wants to check whether the offset is a multiple of the page_size.
Change-Id: I794d021951a28c1cc520b5eea5d500f097721b06 Signed-off-by: Attila Kinali <attila@kinali.ch>
Reviewed-on: http://openocd.zylin.com/482 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
Neil Jensen [Fri, 24 Feb 2012 22:49:07 +0000 (16:49 -0600)]
cfg: Beaglebone/AM335x refactor
Split out functions specific to the AM335x SOC into the target directory and simplified the board config
file. This should allow one to quickly create new configs for boards based on the TI processor family.
Change-Id: I0c3db97950dfa832f1f1918fc10c180f068bba74 Signed-off-by: Neil Jensen <neil30al@gmail.com>
Reviewed-on: http://openocd.zylin.com/489 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Spencer Oliver [Thu, 16 Feb 2012 09:42:06 +0000 (09:42 +0000)]
flash: add stm32f2x async flash loader
This enable the stm32f2x flash driver to use the asynchronous
algorithm support.
Speed increase is as follows:
before - wrote 1048576 bytes from file stm32f4x.bin in 30.453804s (33.625 KiB/s)
after - wrote 1048576 bytes from file stm32f4x.bin in 23.679497s (43.244 KiB/s)
This also fixes a bug that was in the old flash loader.
The old loader waited while bit16 of the status reg was 0, the new
loader waits until this bit is 0 as stated in the flash spec.
Bizarrely this bug did not effect programming on any tested parts.
Change-Id: I3efc94d42cbe81283673a8f4203700638080af6e Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/460 Tested-by: jenkins
Spencer Oliver [Fri, 10 Feb 2012 15:27:27 +0000 (15:27 +0000)]
flash: add stellaris async flash loader
This enable the Stellaris flash driver to use the asynchronous
algorithm support.
Speed increase is as follows:
before - wrote 65536 bytes from file test.bin in 5.486040s (11.666 KiB/s)
after - wrote 65536 bytes from file test.bin in 2.274001s (28.144 KiB/s)
Change-Id: I9004c9aadffa1ae3b0cbf908e6549b5b1f794508 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/403 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Spencer Oliver [Fri, 10 Feb 2012 15:24:52 +0000 (15:24 +0000)]
target: add target async algorithm support
Currently the stm32f1x flash driver uses an asynchronous algorithm
as part of the block flash programming. This greatly speeds up flash
programming as the target is always running.
Moving the async code to the target enable other targets to use this
added functionality.
Change-Id: I8e53f094c2ef7848a7f86ddb9a35b6edbfc8454a Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/402 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Neil Jensen [Sun, 19 Feb 2012 03:37:08 +0000 (21:37 -0600)]
cfg: Beaglebone Support
Added support for the Beaglebone board based on the am335x processor
family. After much trial and error, I was able to configure the
Icepick-D and connect to the processor, halt execution, and run a sample
program. This is a unified config file (it doesn't use any include
statements) and further work needs to be done to split out the icepick-d
configuration to be more generic.
Change-Id: Ia1b8e9f01f56bd4f8c575ba3d0160c248583a15e Signed-off-by: Neil Jensen <neil30al@gmail.com>
Reviewed-on: http://openocd.zylin.com/471 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
target: add function to get number of bytes available in working area
This is a much cleaner solution to the problem of allocating as much
working area as possible than what is currently being done in most/all flash
drivers (which is: try an arbitrary sized chunk, if it fails, pick a smaller
number, rinse and repeat).
Use this function to find out how much working area is available, limit or
restrict that amount at will and then simply allocate it.
Change-Id: Ib7d5d0b7485aed3e0a4fad60c1bedb7dfd16146f Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/446 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The existing allocator couldn't reuse a freed allocation if the sizes
didn't match exactly. That led to problems when for example a flash write
routine had allocated all of the working area to speed up operation. A
subsequent verify pass couldn't allocate space for the checksum algorithm
even though all previous allocations had been freed.
This allocator is marginally more complex, but solves the above problem by
splitting larger free areas to fulfill smaller requests and by merging
released areas into adjacent free areas.
An initial free area, covering the entire specified address range, is set
up on first allocation, and all allocations are split off from (and
ultimately merged into) that one. It can also easily be adapted to support
several disjoint working areas for the same target, by setting up several
initial free areas and slightly modifying the merge code.
Change-Id: I6faaf9801312bb19a4fa4474694a0cd1c6e0ab54 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/445 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
I used the CPUID instead of adding a new argument to the flash bank command
Fixed Type in comments
Add the failsafe return value in device_id
Change-Id: Ieb5a46fc002b5390a0c81bc8b49f6c687036ae1d Signed-off-by: Jonathan Dumaresq <jdumaresq@cimeq.qc.ca>
Reviewed-on: http://openocd.zylin.com/438 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Lars Poeschel [Wed, 26 Oct 2011 14:52:53 +0000 (16:52 +0200)]
add icnova_sam9g45_sodimm support
This adds support for in-circuit icnova sam9g45 sodimm: http://www.ic-board.de/product_info.php?info=p214_ICnova-SAM9G45-SODIMM.html|ICnova
The NAND flash is not yet working.
Freddie Chopin [Thu, 9 Feb 2012 17:37:05 +0000 (18:37 +0100)]
Add init_board documentation
This patch adds init_board concept information to OpenOCD manual.
Additionally a link from init_targets chapter to new chapter about
init_board is added.
Spencer Oliver [Fri, 10 Feb 2012 11:03:05 +0000 (11:03 +0000)]
cfg: fix incorrect STM32L SW-DP id
STM32L ref manual (RM00038 Rev5) states the SW-DP id should be 0x4ba00477.
The correct value from silicon is 0x2ba01477 - the typo has been confirmed by ST.
Change-Id: Ie35a1f13dc5dedc1b148fb219c6974bfa48b537c Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/441 Tested-by: jenkins Reviewed-by: Peter Stuge <peter@stuge.se>
Spencer Oliver [Fri, 10 Feb 2012 12:29:31 +0000 (12:29 +0000)]
cfg: add ST-LINK TRANSPORT config override
This enables the user to override the transport used for st-link.
If JTAG is selected it will also change the default id used to the JTAG id
rather than the SW-DP id.
Change-Id: I4fe352e4932e2f4ec278168e99ba2d2d50fd850a Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/443 Tested-by: jenkins Reviewed-by: Peter Stuge <peter@stuge.se>
Freddie Chopin [Fri, 3 Feb 2012 19:37:45 +0000 (20:37 +0100)]
Add init_board procedure executed after init_targets
This adds init_board procedure that behaves exactly the same as
init_targets - it can be overriden by "next level" scripts. This
procedure is executed after init_targets, allowing common stuff (jtag
chain, memory, flash, ...) to be configured in target script (via
init_target) and leaving rest (like additional memory, reset
configuration, reset-init handlers, ...) to be done in init_board.
This makes init_targets scheme more complete and easier to use - current
board scripts will not need new init_targets, because everything can be
"packed" in init_boards. Moreover it solves the problem of variables
being set in init_targets (executed after init), which were not
accessible by "linear" scripts (parsed before init). All that has to be
done is to enclose all code in board config file in init_board
procedure.
Change-Id: I0736b1ff9873a687966407d62b58ccf29a8e597b Signed-off-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-on: http://openocd.zylin.com/427 Reviewed-by: Chris Morgan <chmorgan@gmail.com> Tested-by: jenkins Reviewed-by: Peter Stuge <peter@stuge.se>
Replace the big stack-allocated buffer with a much bigger heap-allocated.
There was no explanation for the apparently arbitrary chunk size, and
performance was improved by increasing it, leveling out at about 4k.
Timo Ketola [Tue, 17 Jan 2012 08:36:02 +0000 (10:36 +0200)]
i.MX25: Add support for i.MX25 NAND Flash Controller
This patch is based on Erik Ahlén's work on i.MX35 NFC support. Basically it redefines the CCM.RCSR register which is in a different address in i.MX25.
Change-Id: Ia6faf9cb5efae5e564b72ef9a9b7c7f8bfde3ce0 Signed-off-by: Timo Ketola <timo@exertus.fi>
Reviewed-on: http://openocd.zylin.com/383 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
projects / openocd / log