Zachary T Welch [Sat, 21 Nov 2009 06:01:59 +0000 (22:01 -0800)]
remove register_callbacks from jtag interface
Changes the jtag_interface->register_callbacks field to a list of
commands to be registered. Changes callback to invocation of
register_commands() with that command registration list. Removes all
JTAG interface driver register_command callback functions, which the
previous commits had converted into identical calls.
Zachary T Welch [Sat, 21 Nov 2009 03:58:07 +0000 (19:58 -0800)]
at91rm9200: use register_commands()
Use register_commands() with command registration array.
---
This module was broken by previous changes, but no one has complained.
Are there still users for this modules?
Zachary T Welch [Sat, 21 Nov 2009 23:52:12 +0000 (15:52 -0800)]
demonstrate chaining with foo commands
Use the new command registration chaining capabilities to eliminate
the foo_register_commands helper, folding its remaining command
handler setup into the hello_command_handlers registration array.
Zachary T Welch [Sat, 21 Nov 2009 21:59:51 +0000 (13:59 -0800)]
add command registration chaining
Adds the ability to chain registration structures. Modules can define a
command with the 'chain' and 'num_chain' fields defined in their
registration table, and the register_commands() function will initialize
these commands. If the registration record creates a new command, then
the chained commands are created under it; otherwise, they are created
in the same context as the other commands (i.e. the parent argument).
Zachary T Welch [Fri, 20 Nov 2009 21:36:07 +0000 (13:36 -0800)]
command: use register_commands for handlers
Use register_commands() to register low-level command handlers,
adding a builtin_command_handlers declaration that is easy to understand.
Splits help and usage information into their appropriate fields.
Zachary T Welch [Fri, 20 Nov 2009 22:07:28 +0000 (14:07 -0800)]
add command usage, separate from help
Adds the usage command, to display usage information for commands.
The output for this command will remain erronenously empty until
commands are updated to use these new coventions.
Zachary T Welch [Fri, 20 Nov 2009 20:46:06 +0000 (12:46 -0800)]
add register_commands for batch registration
The register_commands API takes multiple commands in one call, allowing
modules to declare and pass a much simpler (and more explicit) array of
command_registration records.
Zachary T Welch [Fri, 20 Nov 2009 19:23:34 +0000 (11:23 -0800)]
add struct command_registration
Add a structure to encapsulate command registration information, rather
than passing them all as parameters. Enables further API changes that
require additional required or optional parameters.
Updates the register_command API and COMMAND_REGISTER macro to use it,
along with their documentation.
David Brownell [Wed, 25 Nov 2009 05:24:44 +0000 (21:24 -0800)]
Cortex-A8: avoid DSCR reads
There was a lot of needless handshaking overhead in the current
Cortex-A8 DCC/ITR operations, since the status read by each step
was discarded rather than letting the next step know it.
This shrinks the handshaking by: (a) passing status along from
previous steps, avoiding re-fetching; which enables the big win
(b) relying on a useful invariant: that the DSCR_INSTR_COMP bit
is set after every call to a DPM method.
A "reg sp_usr" call previously took 17 flushes; now it takes just 9.
This visibly speeds common operations like entry to debug state and
stepping, as well as "arm reg" and so on.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Wed, 25 Nov 2009 05:24:44 +0000 (21:24 -0800)]
Cortex-A8: hook up DPM
This replaces two versions of register access functions. One
was commented out, and seemed to have uncertain intent. The
other was fairly new, and helped motivate the DPM framework
once I observed that the ARM11 was doing the very same ops.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Wed, 25 Nov 2009 05:24:44 +0000 (21:24 -0800)]
Cortex-A8: implement DPM
This implements the DPM interface for Cortex-A8 cores. It
also adds a synchronization operation to the DPM framework,
which is needed by the Cortex-A8 after CPSR writes.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Wed, 25 Nov 2009 05:24:44 +0000 (21:24 -0800)]
Cortex-A8: minor cleanup
Make various functions static, add some comments, report
vector catch as a flavor of DBG_REASON_BREAKPOINT, get
rid of needless/undesirable ARMV4_5_CORE_REG_MODE, etc.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The previous implementation was unnecessarily complex. Get rid of the loops,
let vsnprintf() tell us directly how much storage we need and allocate that. A
second pass writes the actual string. Also add a va_end() that was missing.
This should be much faster for large strings and less wasteful for small ones.
A quirk that has been retained is that some callers patch in a newline at the
end of the returned string and depend on alloc_vprintf to allocate at least
one byte extra.
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Signed-off-by: Zachary T Welch <zw@superlucidity.net>
Zachary T Welch [Thu, 19 Nov 2009 20:02:07 +0000 (12:02 -0800)]
add jtag/usb_common.[ch] files
Begins to consolidate code used by several USB JTAG interfaces.
This first patch provides the required build system changes and
a common jtag_usb_open routine, which will replace the guts for
probing the busses and devices for possible VID/PID matches.
The following patches convert each driver to use it.
David Brownell [Tue, 24 Nov 2009 09:27:29 +0000 (01:27 -0800)]
ARM11: remove old R0..R15/CPSR code
This finishes the basic switchover to the new register code,
for everything except the debug registers. (And maybe we
shouldn't have a cache for *those* which works this way...)
The context save/restore code now uses the new code, but
it's in a slightly different sequence. That should be fine
since the R0/PC/CPSR stuff is all that really matters (and
if we can update those, we can update the rest).
Now there's no longer a way any code can be confused about
which copy of "r1" (etc) to use.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Tue, 24 Nov 2009 09:27:24 +0000 (01:27 -0800)]
ARM11: use standard run_algorithm()
As with single stepping, the previous stuff was needed because
the ARM11 code wasn't using the standard ARM base type and
register access ... but now those mechanisms work, so we can
switch out that special-purpose glue, in favor of the more
thoroughly tested/capable "standard" code.
Fixes a bug in the resume() implementation: it wasn't handling
two of its arguments correctly, preventing the "flash erase_check"
algorithm from working. (This code needs a *subsequent* update
for correct register handling, though... removing the confusion
about which "r2", for example, to use.)
This should resolve some "FIXME" comments too, for Thumb and
processor mode support. It also gets rid of a nasty exit()
call; servers should only have *clean* shutdown paths.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Tue, 24 Nov 2009 09:27:21 +0000 (01:27 -0800)]
ARM11: use standard single step simulation
The previous stuff was needed because the ARM11 code wasn't using
the standard ARM base type and register access ... but now those
mechanisms work, so we can switch out that special-purpose glue.
This should resolve all the "FIXME -- handle Thumb single stepping"
comments too, and properly handle the processor's mode. (Modulo
the issue that this code doesn't yet handle two-byte breakpoints.)
Clarify the comments about the the hardware single stepping. When
we eventually share breakpoint code with Cortex-A8, we can just make
that be the default on cores which support it. We may still want an
override command, not just to facilitate testing but to cope with
"instruction address mismatch" not quite being true single-step.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Tue, 24 Nov 2009 09:27:16 +0000 (01:27 -0800)]
ARM11: partial support for standard ARM register interfaces.
This provides "standard" ARM register support -- with twenty or
more shadow registers on top of what this code now handles, but
properly associated with the various core modes -- parallel to
the current register code. That is, the current code is stilil
managing the "current" registers; the new code shadows them.
You can see all the registers with "arm reg", modify the shadows
like "r8_fiq" or "sp_abt" with "reg", and see them get properly
written back when you step. (Just don't do that with any of the
registers managed by the "old" code ...)
It also switches to using more standard code, relying on those
standard registers, in two places: (a) the poll status display,
which now shows core state (ARM/Thumb/...) and mode (Supervisor,
IRQ, etc); and (b) GDB register access.
So it's not a full migration, there are warts -- every place that
touches the old register cache is a potential bug -- but it's a
small more-or-less-comprehensible step that's even somewhat useful.
Later patches complete the migration.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Tue, 24 Nov 2009 08:14:15 +0000 (00:14 -0800)]
ARM11: remove register "history" debug stuff
This was a private mechanism to snapshot registers before leaving
debug state, and then on reentry to optionally display what changed.
It was coupled to the private register cache, which won't be sticking
around in that form for much longer. Remove (instead of teaching
it how to handle *all* the registers).
(The idea is interesting, but we ought to be able to implement
this in a generic way. Ideally through Tcl scripts that can
automatically be invoked following debug entry...)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Tue, 24 Nov 2009 08:13:58 +0000 (00:13 -0800)]
ARM: new DPM interface
First version of interface for sharing code between ARMv6 and ARMv7a
debug modules ... now the architecture includes debug support. (Not
the same as for the trimmed-down v7m or v6m though!) This is a first
version of an interface that will let the ARM11 and Cortex-A8 support
share code, features, and bugfixes. Based on existing code from both
of those cores.
The ARM v7-AR architecture specification calls this commonality the
"Debug Programmer's Model (DPM)", which seemed to be an appropriate
acronym -- a TLA even! -- for use in our code. Made it so. :)
The initial scope of this just supports register access, and is geared
towards supporting top level "struct arm" mechanisms. Later, things
like breakpoint and watchpoint support should be included.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Sun, 22 Nov 2009 23:51:16 +0000 (15:51 -0800)]
ARM11: remove unused state and exports
For now there's no point in saving this stuff after examine()
checks it out as OK. Ditto exporting symbols that aren't
used outside of the module which defines them. In fact, those
two things needlessly complicate the code...
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Sun, 22 Nov 2009 18:21:48 +0000 (10:21 -0800)]
ARM: use arm_reg_current()
Start using the arm_reg_current() call. This shrinks and speeds
the affected code. It can also prevent some coredumps coming from
invalid CPSR values ... the ARMV4_5_CORE_REG_MODE() macro returns
bogus registers if e.g. "Secure Monitor" mode isn't supported by
the current CPU.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Sun, 22 Nov 2009 11:41:14 +0000 (03:41 -0800)]
ARM: arm_set_cpsr() handles T and J bits
Have arm_set_cpsr() handle the two core state flags, updating
the CPU state. This eliminates code in various debug_entry()
paths, and marginally improves handling of the J bit.
Catch and comment a few holes in the handling of the J bit on
ARM926ejs cores ... it's unlikely our users will care about
Jazelle mode, but we can at least warn of Impending Doom. If
anyone does use it, these breadcrumbs may help them to find
the right path through the code.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Sun, 22 Nov 2009 11:38:34 +0000 (03:38 -0800)]
ARM: define two register utilities
Define arm_reg_current() ... returning handle to a given register,
and encapsulating the current mode's register shadowing. It's got
one current use, for reporting the current register set to GDB.
This will let later patches clean up much ARMV4_5_CORE_REG_MODE()
nastiness, saving a bit of code.
Define and use arm_set_cpsr() ... initially it updates the cached
CPSR and sets up state used by arm_reg_current(), plus any SPSR
handle. (Later: can also set up for T and J bits.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Sun, 22 Nov 2009 11:37:21 +0000 (03:37 -0800)]
ARM: simplify CPSR handling
Stash a pointer to the CPSR in the "struct arm", to help get rid
of the (common) references to its index in the register cache.
This removes almost all references to CPSR offsets outside of the
toplevel ARM code ... except a pair related to the current ARM11
"simulator" logic (which should be removable soonish).
This is a net minor code shrink of a few hundred bytes of object
code, and also makes the code more readable.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Add this to ease debugging why the standard scripts aren't
found on the default script search path in some build/install
enviroments. Especially on Windows it's not straight forward
where openocd actually looks for the scripts.
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Sat, 21 Nov 2009 00:27:24 +0000 (16:27 -0800)]
ARM: pass 'struct reg *' to register r/w routines
Implementations need to access the register struct they modify;
make it easier and less error-prone to identify the instance.
(This removes over 10% of the ARMV4_5_CORE_REG_MODE nastiness...)
Plus some minor fixes noted when making these updates: ARM7/ARM9
accessor methods should be static; don't leave CPSR wrongly marked
"dirty"; note significant XScale omissions in register handling;
and have armv4_5_build_reg_cache() record its result.
Rename "struct armv4_5_core_reg" as "struct arm_reg"; it's used
for more than those older architecture generations.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>