From 022a99d8b2f84e6bda44e6dcfd1748219b665143 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 15 Aug 2015 13:17:49 +0200 Subject: [PATCH] sunxi_nand_spl: Add support for sun4i and sun5i SoCs Other then having a few less chip-select lines the nand controller on sun4i, sun5i and sun7i is identical. Note this patch also muxes GPC7 to the NAND on sun7i where as before it was not muxed this way. GPC7 is a standard NAND pin, so it should always be muxed to the NAND when in use. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- board/sunxi/board.c | 12 +++++++++--- drivers/mtd/nand/Kconfig | 4 ++-- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 1ebd0a423d..d411e96c76 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -112,13 +112,19 @@ int dram_init(void) static void nand_pinmux_setup(void) { unsigned int pin; - for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(6); pin++) - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); - for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(22); pin++) + for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); +#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I + for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++) + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); +#endif + /* sun4i / sun7i do have a PC23, but it is not used for nand, + * only sun7i has a PC24 */ +#ifdef CONFIG_MACH_SUN7I sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND); +#endif } static void nand_clock_setup(void) diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 28597f0c8b..8fac5e873b 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -93,8 +93,8 @@ config SPL_NAND_DENALI for use on SPL. config SPL_NAND_SUNXI - bool "Support for NAND on Allwinner A20 in SPL" - depends on MACH_SUN7I + bool "Support for NAND on Allwinner SoCs in SPL" + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I select SYS_NAND_SELF_INIT ---help--- Enable support for NAND. This option allows SPL to read from -- 2.39.5