From 060f9bf57b1dc1f9260bc1b999d054141b87d7d2 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 24 Jul 2015 09:22:11 +0200 Subject: [PATCH] ARM: bcm283x: Define CONFIG_SYS_CACHELINE_SIZE The cacheline is always 32 bytes for arm1176 CPUs, so define it at board config level for cache handling code. The ARM Cortex-A7 has a dcache line size of 64 bytes. Signed-off-by: Alexander Stein Acked-by: Stephen Warren Tested-by: Stephen Warren --- include/configs/rpi.h | 2 ++ include/configs/rpi_2.h | 1 + 2 files changed, 3 insertions(+) diff --git a/include/configs/rpi.h b/include/configs/rpi.h index ab2f4db39f..86422e390d 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -7,6 +7,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_CACHELINE_SIZE 32 + #include "rpi-common.h" #endif diff --git a/include/configs/rpi_2.h b/include/configs/rpi_2.h index 2e7e74fd56..13dc8de143 100644 --- a/include/configs/rpi_2.h +++ b/include/configs/rpi_2.h @@ -9,6 +9,7 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BCM2836 +#define CONFIG_SYS_CACHELINE_SIZE 64 #include "rpi-common.h" -- 2.39.5